pwrseq_regs.h

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/******************************************************************************
 *
 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 
 * Analog Devices, Inc.),
 * Copyright (C) 2023-2024 Analog Devices, Inc.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 ******************************************************************************/
 
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_PWRSEQ_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_PWRSEQ_REGS_H_
 
/* **** Includes **** */
#include <stdint.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
#if defined (__ICCARM__)
  #pragma system_include
#endif
 
#if defined (__CC_ARM)
  #pragma anon_unions
#endif
/*
    If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I  volatile const
#endif
#ifndef __O
#define __O  volatile
#endif
#ifndef __R
#define __R  volatile const
#endif
 
/* **** Definitions **** */
 
typedef struct {
    __IO uint32_t ctrl;                 
    __IO uint32_t gpio0_wk_fl;          
    __IO uint32_t gpio0_wk_en;          
    __IO uint32_t gpio1_wk_fl;          
    __IO uint32_t gpio1_wk_en;          
    __IO uint32_t gpio2_wk_fl;          
    __IO uint32_t gpio2_wk_en;          
    __IO uint32_t gpio3_wk_fl;          
    __IO uint32_t gpio3_wk_en;          
    __R  uint32_t rsv_0x24_0x2f[3];
    __IO uint32_t usb_wk_fl;            
    __IO uint32_t usb_wk_en;            
    __R  uint32_t rsv_0x38_0x3f[2];
    __IO uint32_t mem_pwr;              
} mxc_pwrseq_regs_t;
 
/* Register offsets for module PWRSEQ */
#define MXC_R_PWRSEQ_CTRL                  ((uint32_t)0x00000000UL) 
#define MXC_R_PWRSEQ_GPIO0_WK_FL           ((uint32_t)0x00000004UL) 
#define MXC_R_PWRSEQ_GPIO0_WK_EN           ((uint32_t)0x00000008UL) 
#define MXC_R_PWRSEQ_GPIO1_WK_FL           ((uint32_t)0x0000000CUL) 
#define MXC_R_PWRSEQ_GPIO1_WK_EN           ((uint32_t)0x00000010UL) 
#define MXC_R_PWRSEQ_GPIO2_WK_FL           ((uint32_t)0x00000014UL) 
#define MXC_R_PWRSEQ_GPIO2_WK_EN           ((uint32_t)0x00000018UL) 
#define MXC_R_PWRSEQ_GPIO3_WK_FL           ((uint32_t)0x0000001CUL) 
#define MXC_R_PWRSEQ_GPIO3_WK_EN           ((uint32_t)0x00000020UL) 
#define MXC_R_PWRSEQ_USB_WK_FL             ((uint32_t)0x00000030UL) 
#define MXC_R_PWRSEQ_USB_WK_EN             ((uint32_t)0x00000034UL) 
#define MXC_R_PWRSEQ_MEM_PWR               ((uint32_t)0x00000040UL) 
#define MXC_F_PWRSEQ_CTRL_RAMRET_POS                   0 
#define MXC_F_PWRSEQ_CTRL_RAMRET                       ((uint32_t)(0x3UL << MXC_F_PWRSEQ_CTRL_RAMRET_POS)) 
#define MXC_V_PWRSEQ_CTRL_RAMRET_DIS                   ((uint32_t)0x0UL) 
#define MXC_S_PWRSEQ_CTRL_RAMRET_DIS                   (MXC_V_PWRSEQ_CTRL_RAMRET_DIS << MXC_F_PWRSEQ_CTRL_RAMRET_POS) 
#define MXC_V_PWRSEQ_CTRL_RAMRET_EN1                   ((uint32_t)0x1UL) 
#define MXC_S_PWRSEQ_CTRL_RAMRET_EN1                   (MXC_V_PWRSEQ_CTRL_RAMRET_EN1 << MXC_F_PWRSEQ_CTRL_RAMRET_POS) 
#define MXC_V_PWRSEQ_CTRL_RAMRET_EN2                   ((uint32_t)0x2UL) 
#define MXC_S_PWRSEQ_CTRL_RAMRET_EN2                   (MXC_V_PWRSEQ_CTRL_RAMRET_EN2 << MXC_F_PWRSEQ_CTRL_RAMRET_POS) 
#define MXC_V_PWRSEQ_CTRL_RAMRET_EN3                   ((uint32_t)0x3UL) 
#define MXC_S_PWRSEQ_CTRL_RAMRET_EN3                   (MXC_V_PWRSEQ_CTRL_RAMRET_EN3 << MXC_F_PWRSEQ_CTRL_RAMRET_POS) 
#define MXC_F_PWRSEQ_CTRL_RREGEN_POS                   8 
#define MXC_F_PWRSEQ_CTRL_RREGEN                       ((uint32_t)(0x1UL << MXC_F_PWRSEQ_CTRL_RREGEN_POS)) 
#define MXC_V_PWRSEQ_CTRL_RREGEN_DIS                   ((uint32_t)0x0UL) 
#define MXC_S_PWRSEQ_CTRL_RREGEN_DIS                   (MXC_V_PWRSEQ_CTRL_RREGEN_DIS << MXC_F_PWRSEQ_CTRL_RREGEN_POS) 
#define MXC_V_PWRSEQ_CTRL_RREGEN_EN                    ((uint32_t)0x1UL) 
#define MXC_S_PWRSEQ_CTRL_RREGEN_EN                    (MXC_V_PWRSEQ_CTRL_RREGEN_EN << MXC_F_PWRSEQ_CTRL_RREGEN_POS) 
#define MXC_F_PWRSEQ_CTRL_BKGRND_POS                   9 
#define MXC_F_PWRSEQ_CTRL_BKGRND                       ((uint32_t)(0x1UL << MXC_F_PWRSEQ_CTRL_BKGRND_POS)) 
#define MXC_V_PWRSEQ_CTRL_BKGRND_DIS                   ((uint32_t)0x0UL) 
#define MXC_S_PWRSEQ_CTRL_BKGRND_DIS                   (MXC_V_PWRSEQ_CTRL_BKGRND_DIS << MXC_F_PWRSEQ_CTRL_BKGRND_POS) 
#define MXC_V_PWRSEQ_CTRL_BKGRND_EN                    ((uint32_t)0x1UL) 
#define MXC_S_PWRSEQ_CTRL_BKGRND_EN                    (MXC_V_PWRSEQ_CTRL_BKGRND_EN << MXC_F_PWRSEQ_CTRL_BKGRND_POS) 
#define MXC_F_PWRSEQ_CTRL_FWKM_POS                     10 
#define MXC_F_PWRSEQ_CTRL_FWKM                         ((uint32_t)(0x1UL << MXC_F_PWRSEQ_CTRL_FWKM_POS)) 
#define MXC_V_PWRSEQ_CTRL_FWKM_DIS                     ((uint32_t)0x0UL) 
#define MXC_S_PWRSEQ_CTRL_FWKM_DIS                     (MXC_V_PWRSEQ_CTRL_FWKM_DIS << MXC_F_PWRSEQ_CTRL_FWKM_POS) 
#define MXC_V_PWRSEQ_CTRL_FWKM_EN                      ((uint32_t)0x1UL) 
#define MXC_S_PWRSEQ_CTRL_FWKM_EN                      (MXC_V_PWRSEQ_CTRL_FWKM_EN << MXC_F_PWRSEQ_CTRL_FWKM_POS) 
#define MXC_F_PWRSEQ_CTRL_BGOFF_POS                    11 
#define MXC_F_PWRSEQ_CTRL_BGOFF                        ((uint32_t)(0x1UL << MXC_F_PWRSEQ_CTRL_BGOFF_POS)) 
#define MXC_V_PWRSEQ_CTRL_BGOFF_ON                     ((uint32_t)0x0UL) 
#define MXC_S_PWRSEQ_CTRL_BGOFF_ON                     (MXC_V_PWRSEQ_CTRL_BGOFF_ON << MXC_F_PWRSEQ_CTRL_BGOFF_POS) 
#define MXC_V_PWRSEQ_CTRL_BGOFF_OFF                    ((uint32_t)0x1UL) 
#define MXC_S_PWRSEQ_CTRL_BGOFF_OFF                    (MXC_V_PWRSEQ_CTRL_BGOFF_OFF << MXC_F_PWRSEQ_CTRL_BGOFF_POS) 
#define MXC_F_PWRSEQ_CTRL_PORVCOREMD_POS               12 
#define MXC_F_PWRSEQ_CTRL_PORVCOREMD                   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_CTRL_PORVCOREMD_POS)) 
#define MXC_V_PWRSEQ_CTRL_PORVCOREMD_EN                ((uint32_t)0x0UL) 
#define MXC_S_PWRSEQ_CTRL_PORVCOREMD_EN                (MXC_V_PWRSEQ_CTRL_PORVCOREMD_EN << MXC_F_PWRSEQ_CTRL_PORVCOREMD_POS) 
#define MXC_V_PWRSEQ_CTRL_PORVCOREMD_DIS               ((uint32_t)0x1UL) 
#define MXC_S_PWRSEQ_CTRL_PORVCOREMD_DIS               (MXC_V_PWRSEQ_CTRL_PORVCOREMD_DIS << MXC_F_PWRSEQ_CTRL_PORVCOREMD_POS) 
#define MXC_F_PWRSEQ_CTRL_VCOREMD_POS                  20 
#define MXC_F_PWRSEQ_CTRL_VCOREMD                      ((uint32_t)(0x1UL << MXC_F_PWRSEQ_CTRL_VCOREMD_POS)) 
#define MXC_V_PWRSEQ_CTRL_VCOREMD_EN                   ((uint32_t)0x0UL) 
#define MXC_S_PWRSEQ_CTRL_VCOREMD_EN                   (MXC_V_PWRSEQ_CTRL_VCOREMD_EN << MXC_F_PWRSEQ_CTRL_VCOREMD_POS) 
#define MXC_V_PWRSEQ_CTRL_VCOREMD_DIS                  ((uint32_t)0x1UL) 
#define MXC_S_PWRSEQ_CTRL_VCOREMD_DIS                  (MXC_V_PWRSEQ_CTRL_VCOREMD_DIS << MXC_F_PWRSEQ_CTRL_VCOREMD_POS) 
#define MXC_F_PWRSEQ_CTRL_VRTCMD_POS                   21 
#define MXC_F_PWRSEQ_CTRL_VRTCMD                       ((uint32_t)(0x1UL << MXC_F_PWRSEQ_CTRL_VRTCMD_POS)) 
#define MXC_V_PWRSEQ_CTRL_VRTCMD_EN                    ((uint32_t)0x0UL) 
#define MXC_S_PWRSEQ_CTRL_VRTCMD_EN                    (MXC_V_PWRSEQ_CTRL_VRTCMD_EN << MXC_F_PWRSEQ_CTRL_VRTCMD_POS) 
#define MXC_V_PWRSEQ_CTRL_VRTCMD_DIS                   ((uint32_t)0x1UL) 
#define MXC_S_PWRSEQ_CTRL_VRTCMD_DIS                   (MXC_V_PWRSEQ_CTRL_VRTCMD_DIS << MXC_F_PWRSEQ_CTRL_VRTCMD_POS) 
#define MXC_F_PWRSEQ_CTRL_VDDAMD_POS                   22 
#define MXC_F_PWRSEQ_CTRL_VDDAMD                       ((uint32_t)(0x1UL << MXC_F_PWRSEQ_CTRL_VDDAMD_POS)) 
#define MXC_V_PWRSEQ_CTRL_VDDAMD_EN                    ((uint32_t)0x0UL) 
#define MXC_S_PWRSEQ_CTRL_VDDAMD_EN                    (MXC_V_PWRSEQ_CTRL_VDDAMD_EN << MXC_F_PWRSEQ_CTRL_VDDAMD_POS) 
#define MXC_V_PWRSEQ_CTRL_VDDAMD_DIS                   ((uint32_t)0x1UL) 
#define MXC_S_PWRSEQ_CTRL_VDDAMD_DIS                   (MXC_V_PWRSEQ_CTRL_VDDAMD_DIS << MXC_F_PWRSEQ_CTRL_VDDAMD_POS) 
#define MXC_F_PWRSEQ_CTRL_VDDIOMD_POS                  23 
#define MXC_F_PWRSEQ_CTRL_VDDIOMD                      ((uint32_t)(0x1UL << MXC_F_PWRSEQ_CTRL_VDDIOMD_POS)) 
#define MXC_V_PWRSEQ_CTRL_VDDIOMD_EN                   ((uint32_t)0x0UL) 
#define MXC_S_PWRSEQ_CTRL_VDDIOMD_EN                   (MXC_V_PWRSEQ_CTRL_VDDIOMD_EN << MXC_F_PWRSEQ_CTRL_VDDIOMD_POS) 
#define MXC_V_PWRSEQ_CTRL_VDDIOMD_DIS                  ((uint32_t)0x1UL) 
#define MXC_S_PWRSEQ_CTRL_VDDIOMD_DIS                  (MXC_V_PWRSEQ_CTRL_VDDIOMD_DIS << MXC_F_PWRSEQ_CTRL_VDDIOMD_POS) 
#define MXC_F_PWRSEQ_CTRL_VDDIOHMD_POS                 24 
#define MXC_F_PWRSEQ_CTRL_VDDIOHMD                     ((uint32_t)(0x1UL << MXC_F_PWRSEQ_CTRL_VDDIOHMD_POS)) 
#define MXC_V_PWRSEQ_CTRL_VDDIOHMD_EN                  ((uint32_t)0x0UL) 
#define MXC_S_PWRSEQ_CTRL_VDDIOHMD_EN                  (MXC_V_PWRSEQ_CTRL_VDDIOHMD_EN << MXC_F_PWRSEQ_CTRL_VDDIOHMD_POS) 
#define MXC_V_PWRSEQ_CTRL_VDDIOHMD_DIS                 ((uint32_t)0x1UL) 
#define MXC_S_PWRSEQ_CTRL_VDDIOHMD_DIS                 (MXC_V_PWRSEQ_CTRL_VDDIOHMD_DIS << MXC_F_PWRSEQ_CTRL_VDDIOHMD_POS) 
#define MXC_F_PWRSEQ_CTRL_PORVDDIOMD_POS               25 
#define MXC_F_PWRSEQ_CTRL_PORVDDIOMD                   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_CTRL_PORVDDIOMD_POS)) 
#define MXC_V_PWRSEQ_CTRL_PORVDDIOMD_EN                ((uint32_t)0x0UL) 
#define MXC_S_PWRSEQ_CTRL_PORVDDIOMD_EN                (MXC_V_PWRSEQ_CTRL_PORVDDIOMD_EN << MXC_F_PWRSEQ_CTRL_PORVDDIOMD_POS) 
#define MXC_V_PWRSEQ_CTRL_PORVDDIOMD_DIS               ((uint32_t)0x1UL) 
#define MXC_S_PWRSEQ_CTRL_PORVDDIOMD_DIS               (MXC_V_PWRSEQ_CTRL_PORVDDIOMD_DIS << MXC_F_PWRSEQ_CTRL_PORVDDIOMD_POS) 
#define MXC_F_PWRSEQ_CTRL_PORVDDIOHMD_POS              26 
#define MXC_F_PWRSEQ_CTRL_PORVDDIOHMD                  ((uint32_t)(0x1UL << MXC_F_PWRSEQ_CTRL_PORVDDIOHMD_POS)) 
#define MXC_V_PWRSEQ_CTRL_PORVDDIOHMD_EN               ((uint32_t)0x0UL) 
#define MXC_S_PWRSEQ_CTRL_PORVDDIOHMD_EN               (MXC_V_PWRSEQ_CTRL_PORVDDIOHMD_EN << MXC_F_PWRSEQ_CTRL_PORVDDIOHMD_POS) 
#define MXC_V_PWRSEQ_CTRL_PORVDDIOHMD_DIS              ((uint32_t)0x1UL) 
#define MXC_S_PWRSEQ_CTRL_PORVDDIOHMD_DIS              (MXC_V_PWRSEQ_CTRL_PORVDDIOHMD_DIS << MXC_F_PWRSEQ_CTRL_PORVDDIOHMD_POS) 
#define MXC_F_PWRSEQ_CTRL_VDDBMD_POS                   27 
#define MXC_F_PWRSEQ_CTRL_VDDBMD                       ((uint32_t)(0x1UL << MXC_F_PWRSEQ_CTRL_VDDBMD_POS)) 
#define MXC_V_PWRSEQ_CTRL_VDDBMD_EN                    ((uint32_t)0x0UL) 
#define MXC_S_PWRSEQ_CTRL_VDDBMD_EN                    (MXC_V_PWRSEQ_CTRL_VDDBMD_EN << MXC_F_PWRSEQ_CTRL_VDDBMD_POS) 
#define MXC_V_PWRSEQ_CTRL_VDDBMD_DIS                   ((uint32_t)0x1UL) 
#define MXC_S_PWRSEQ_CTRL_VDDBMD_DIS                   (MXC_V_PWRSEQ_CTRL_VDDBMD_DIS << MXC_F_PWRSEQ_CTRL_VDDBMD_POS) 
#define MXC_F_PWRSEQ_GPIO0_WK_FL_WAKEST_POS            0 
#define MXC_F_PWRSEQ_GPIO0_WK_FL_WAKEST                ((uint32_t)(0xFFFFFFFFUL << MXC_F_PWRSEQ_GPIO0_WK_FL_WAKEST_POS)) 
#define MXC_F_PWRSEQ_GPIO0_WK_EN_WAKEEN_POS            0 
#define MXC_F_PWRSEQ_GPIO0_WK_EN_WAKEEN                ((uint32_t)(0xFFFFFFFFUL << MXC_F_PWRSEQ_GPIO0_WK_EN_WAKEEN_POS)) 
#define MXC_F_PWRSEQ_GPIO1_WK_FL_WAKEST_POS            0 
#define MXC_F_PWRSEQ_GPIO1_WK_FL_WAKEST                ((uint32_t)(0xFFFFFFFFUL << MXC_F_PWRSEQ_GPIO1_WK_FL_WAKEST_POS)) 
#define MXC_F_PWRSEQ_GPIO1_WK_EN_WAKEEN_POS            0 
#define MXC_F_PWRSEQ_GPIO1_WK_EN_WAKEEN                ((uint32_t)(0xFFFFFFFFUL << MXC_F_PWRSEQ_GPIO1_WK_EN_WAKEEN_POS)) 
#define MXC_F_PWRSEQ_GPIO2_WK_FL_WAKEST_POS            0 
#define MXC_F_PWRSEQ_GPIO2_WK_FL_WAKEST                ((uint32_t)(0xFFFFFFFFUL << MXC_F_PWRSEQ_GPIO2_WK_FL_WAKEST_POS)) 
#define MXC_F_PWRSEQ_GPIO2_WK_EN_WAKEEN_POS            0 
#define MXC_F_PWRSEQ_GPIO2_WK_EN_WAKEEN                ((uint32_t)(0xFFFFFFFFUL << MXC_F_PWRSEQ_GPIO2_WK_EN_WAKEEN_POS)) 
#define MXC_F_PWRSEQ_GPIO3_WK_FL_WAKEST_POS            0 
#define MXC_F_PWRSEQ_GPIO3_WK_FL_WAKEST                ((uint32_t)(0x3FFUL << MXC_F_PWRSEQ_GPIO3_WK_FL_WAKEST_POS)) 
#define MXC_F_PWRSEQ_GPIO3_WK_EN_WAKEEN_POS            0 
#define MXC_F_PWRSEQ_GPIO3_WK_EN_WAKEEN                ((uint32_t)(0x3FFUL << MXC_F_PWRSEQ_GPIO3_WK_EN_WAKEEN_POS)) 
#define MXC_F_PWRSEQ_USB_WK_FL_USBLSWKST_POS           0 
#define MXC_F_PWRSEQ_USB_WK_FL_USBLSWKST               ((uint32_t)(0x3UL << MXC_F_PWRSEQ_USB_WK_FL_USBLSWKST_POS)) 
#define MXC_V_PWRSEQ_USB_WK_FL_USBLSWKST_DPLUS         ((uint32_t)0x0UL) 
#define MXC_S_PWRSEQ_USB_WK_FL_USBLSWKST_DPLUS         (MXC_V_PWRSEQ_USB_WK_FL_USBLSWKST_DPLUS << MXC_F_PWRSEQ_USB_WK_FL_USBLSWKST_POS) 
#define MXC_V_PWRSEQ_USB_WK_FL_USBLSWKST_DMINUS        ((uint32_t)0x1UL) 
#define MXC_S_PWRSEQ_USB_WK_FL_USBLSWKST_DMINUS        (MXC_V_PWRSEQ_USB_WK_FL_USBLSWKST_DMINUS << MXC_F_PWRSEQ_USB_WK_FL_USBLSWKST_POS) 
#define MXC_F_PWRSEQ_USB_WK_FL_USBVBUSWKST_POS         2 
#define MXC_F_PWRSEQ_USB_WK_FL_USBVBUSWKST             ((uint32_t)(0x1UL << MXC_F_PWRSEQ_USB_WK_FL_USBVBUSWKST_POS)) 
#define MXC_V_PWRSEQ_USB_WK_FL_USBVBUSWKST_NORMAL      ((uint32_t)0x0UL) 
#define MXC_S_PWRSEQ_USB_WK_FL_USBVBUSWKST_NORMAL      (MXC_V_PWRSEQ_USB_WK_FL_USBVBUSWKST_NORMAL << MXC_F_PWRSEQ_USB_WK_FL_USBVBUSWKST_POS) 
#define MXC_V_PWRSEQ_USB_WK_FL_USBVBUSWKST_STCHNG      ((uint32_t)0x1UL) 
#define MXC_S_PWRSEQ_USB_WK_FL_USBVBUSWKST_STCHNG      (MXC_V_PWRSEQ_USB_WK_FL_USBVBUSWKST_STCHNG << MXC_F_PWRSEQ_USB_WK_FL_USBVBUSWKST_POS) 
#define MXC_F_PWRSEQ_USB_WK_EN_USBLSWKEN_POS           0 
#define MXC_F_PWRSEQ_USB_WK_EN_USBLSWKEN               ((uint32_t)(0x3UL << MXC_F_PWRSEQ_USB_WK_EN_USBLSWKEN_POS)) 
#define MXC_V_PWRSEQ_USB_WK_EN_USBLSWKEN_DIS           ((uint32_t)0x0UL) 
#define MXC_S_PWRSEQ_USB_WK_EN_USBLSWKEN_DIS           (MXC_V_PWRSEQ_USB_WK_EN_USBLSWKEN_DIS << MXC_F_PWRSEQ_USB_WK_EN_USBLSWKEN_POS) 
#define MXC_V_PWRSEQ_USB_WK_EN_USBLSWKEN_EN            ((uint32_t)0x3UL) 
#define MXC_S_PWRSEQ_USB_WK_EN_USBLSWKEN_EN            (MXC_V_PWRSEQ_USB_WK_EN_USBLSWKEN_EN << MXC_F_PWRSEQ_USB_WK_EN_USBLSWKEN_POS) 
#define MXC_F_PWRSEQ_USB_WK_EN_USBVBUSWKEN_POS         2 
#define MXC_F_PWRSEQ_USB_WK_EN_USBVBUSWKEN             ((uint32_t)(0x1UL << MXC_F_PWRSEQ_USB_WK_EN_USBVBUSWKEN_POS)) 
#define MXC_V_PWRSEQ_USB_WK_EN_USBVBUSWKEN_DIS         ((uint32_t)0x0UL) 
#define MXC_S_PWRSEQ_USB_WK_EN_USBVBUSWKEN_DIS         (MXC_V_PWRSEQ_USB_WK_EN_USBVBUSWKEN_DIS << MXC_F_PWRSEQ_USB_WK_EN_USBVBUSWKEN_POS) 
#define MXC_V_PWRSEQ_USB_WK_EN_USBVBUSWKEN_EN          ((uint32_t)0x1UL) 
#define MXC_S_PWRSEQ_USB_WK_EN_USBVBUSWKEN_EN          (MXC_V_PWRSEQ_USB_WK_EN_USBVBUSWKEN_EN << MXC_F_PWRSEQ_USB_WK_EN_USBVBUSWKEN_POS) 
#define MXC_F_PWRSEQ_MEM_PWR_SRAM0SD_POS               0 
#define MXC_F_PWRSEQ_MEM_PWR_SRAM0SD                   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_MEM_PWR_SRAM0SD_POS)) 
#define MXC_V_PWRSEQ_MEM_PWR_SRAM0SD_NORMAL            ((uint32_t)0x0UL) 
#define MXC_S_PWRSEQ_MEM_PWR_SRAM0SD_NORMAL            (MXC_V_PWRSEQ_MEM_PWR_SRAM0SD_NORMAL << MXC_F_PWRSEQ_MEM_PWR_SRAM0SD_POS) 
#define MXC_V_PWRSEQ_MEM_PWR_SRAM0SD_SHUTDOWN          ((uint32_t)0x1UL) 
#define MXC_S_PWRSEQ_MEM_PWR_SRAM0SD_SHUTDOWN          (MXC_V_PWRSEQ_MEM_PWR_SRAM0SD_SHUTDOWN << MXC_F_PWRSEQ_MEM_PWR_SRAM0SD_POS) 
#define MXC_F_PWRSEQ_MEM_PWR_SRAM1SD_POS               1 
#define MXC_F_PWRSEQ_MEM_PWR_SRAM1SD                   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_MEM_PWR_SRAM1SD_POS)) 
#define MXC_V_PWRSEQ_MEM_PWR_SRAM1SD_NORMAL            ((uint32_t)0x0UL) 
#define MXC_S_PWRSEQ_MEM_PWR_SRAM1SD_NORMAL            (MXC_V_PWRSEQ_MEM_PWR_SRAM1SD_NORMAL << MXC_F_PWRSEQ_MEM_PWR_SRAM1SD_POS) 
#define MXC_V_PWRSEQ_MEM_PWR_SRAM1SD_SHUTDOWN          ((uint32_t)0x1UL) 
#define MXC_S_PWRSEQ_MEM_PWR_SRAM1SD_SHUTDOWN          (MXC_V_PWRSEQ_MEM_PWR_SRAM1SD_SHUTDOWN << MXC_F_PWRSEQ_MEM_PWR_SRAM1SD_POS) 
#define MXC_F_PWRSEQ_MEM_PWR_SRAM2SD_POS               2 
#define MXC_F_PWRSEQ_MEM_PWR_SRAM2SD                   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_MEM_PWR_SRAM2SD_POS)) 
#define MXC_V_PWRSEQ_MEM_PWR_SRAM2SD_NORMAL            ((uint32_t)0x0UL) 
#define MXC_S_PWRSEQ_MEM_PWR_SRAM2SD_NORMAL            (MXC_V_PWRSEQ_MEM_PWR_SRAM2SD_NORMAL << MXC_F_PWRSEQ_MEM_PWR_SRAM2SD_POS) 
#define MXC_V_PWRSEQ_MEM_PWR_SRAM2SD_SHUTDOWN          ((uint32_t)0x1UL) 
#define MXC_S_PWRSEQ_MEM_PWR_SRAM2SD_SHUTDOWN          (MXC_V_PWRSEQ_MEM_PWR_SRAM2SD_SHUTDOWN << MXC_F_PWRSEQ_MEM_PWR_SRAM2SD_POS) 
#define MXC_F_PWRSEQ_MEM_PWR_SRAM3SD_POS               3 
#define MXC_F_PWRSEQ_MEM_PWR_SRAM3SD                   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_MEM_PWR_SRAM3SD_POS)) 
#define MXC_V_PWRSEQ_MEM_PWR_SRAM3SD_NORMAL            ((uint32_t)0x0UL) 
#define MXC_S_PWRSEQ_MEM_PWR_SRAM3SD_NORMAL            (MXC_V_PWRSEQ_MEM_PWR_SRAM3SD_NORMAL << MXC_F_PWRSEQ_MEM_PWR_SRAM3SD_POS) 
#define MXC_V_PWRSEQ_MEM_PWR_SRAM3SD_SHUTDOWN          ((uint32_t)0x1UL) 
#define MXC_S_PWRSEQ_MEM_PWR_SRAM3SD_SHUTDOWN          (MXC_V_PWRSEQ_MEM_PWR_SRAM3SD_SHUTDOWN << MXC_F_PWRSEQ_MEM_PWR_SRAM3SD_POS) 
#define MXC_F_PWRSEQ_MEM_PWR_SRAM4SD_POS               4 
#define MXC_F_PWRSEQ_MEM_PWR_SRAM4SD                   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_MEM_PWR_SRAM4SD_POS)) 
#define MXC_V_PWRSEQ_MEM_PWR_SRAM4SD_NORMAL            ((uint32_t)0x0UL) 
#define MXC_S_PWRSEQ_MEM_PWR_SRAM4SD_NORMAL            (MXC_V_PWRSEQ_MEM_PWR_SRAM4SD_NORMAL << MXC_F_PWRSEQ_MEM_PWR_SRAM4SD_POS) 
#define MXC_V_PWRSEQ_MEM_PWR_SRAM4SD_SHUTDOWN          ((uint32_t)0x1UL) 
#define MXC_S_PWRSEQ_MEM_PWR_SRAM4SD_SHUTDOWN          (MXC_V_PWRSEQ_MEM_PWR_SRAM4SD_SHUTDOWN << MXC_F_PWRSEQ_MEM_PWR_SRAM4SD_POS) 
#define MXC_F_PWRSEQ_MEM_PWR_SRAM5SD_POS               5 
#define MXC_F_PWRSEQ_MEM_PWR_SRAM5SD                   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_MEM_PWR_SRAM5SD_POS)) 
#define MXC_V_PWRSEQ_MEM_PWR_SRAM5SD_NORMAL            ((uint32_t)0x0UL) 
#define MXC_S_PWRSEQ_MEM_PWR_SRAM5SD_NORMAL            (MXC_V_PWRSEQ_MEM_PWR_SRAM5SD_NORMAL << MXC_F_PWRSEQ_MEM_PWR_SRAM5SD_POS) 
#define MXC_V_PWRSEQ_MEM_PWR_SRAM5SD_SHUTDOWN          ((uint32_t)0x1UL) 
#define MXC_S_PWRSEQ_MEM_PWR_SRAM5SD_SHUTDOWN          (MXC_V_PWRSEQ_MEM_PWR_SRAM5SD_SHUTDOWN << MXC_F_PWRSEQ_MEM_PWR_SRAM5SD_POS) 
#define MXC_F_PWRSEQ_MEM_PWR_SRAM6SD_POS               6 
#define MXC_F_PWRSEQ_MEM_PWR_SRAM6SD                   ((uint32_t)(0x1UL << MXC_F_PWRSEQ_MEM_PWR_SRAM6SD_POS)) 
#define MXC_V_PWRSEQ_MEM_PWR_SRAM6SD_NORMAL            ((uint32_t)0x0UL) 
#define MXC_S_PWRSEQ_MEM_PWR_SRAM6SD_NORMAL            (MXC_V_PWRSEQ_MEM_PWR_SRAM6SD_NORMAL << MXC_F_PWRSEQ_MEM_PWR_SRAM6SD_POS) 
#define MXC_V_PWRSEQ_MEM_PWR_SRAM6SD_SHUTDOWN          ((uint32_t)0x1UL) 
#define MXC_S_PWRSEQ_MEM_PWR_SRAM6SD_SHUTDOWN          (MXC_V_PWRSEQ_MEM_PWR_SRAM6SD_SHUTDOWN << MXC_F_PWRSEQ_MEM_PWR_SRAM6SD_POS) 
#define MXC_F_PWRSEQ_MEM_PWR_ICACHESD_POS              7 
#define MXC_F_PWRSEQ_MEM_PWR_ICACHESD                  ((uint32_t)(0x1UL << MXC_F_PWRSEQ_MEM_PWR_ICACHESD_POS)) 
#define MXC_V_PWRSEQ_MEM_PWR_ICACHESD_NORMAL           ((uint32_t)0x0UL) 
#define MXC_S_PWRSEQ_MEM_PWR_ICACHESD_NORMAL           (MXC_V_PWRSEQ_MEM_PWR_ICACHESD_NORMAL << MXC_F_PWRSEQ_MEM_PWR_ICACHESD_POS) 
#define MXC_V_PWRSEQ_MEM_PWR_ICACHESD_SHUTDOWN         ((uint32_t)0x1UL) 
#define MXC_S_PWRSEQ_MEM_PWR_ICACHESD_SHUTDOWN         (MXC_V_PWRSEQ_MEM_PWR_ICACHESD_SHUTDOWN << MXC_F_PWRSEQ_MEM_PWR_ICACHESD_POS) 
#define MXC_F_PWRSEQ_MEM_PWR_ICACHEXIPSD_POS           8 
#define MXC_F_PWRSEQ_MEM_PWR_ICACHEXIPSD               ((uint32_t)(0x1UL << MXC_F_PWRSEQ_MEM_PWR_ICACHEXIPSD_POS)) 
#define MXC_V_PWRSEQ_MEM_PWR_ICACHEXIPSD_NORMAL        ((uint32_t)0x0UL) 
#define MXC_S_PWRSEQ_MEM_PWR_ICACHEXIPSD_NORMAL        (MXC_V_PWRSEQ_MEM_PWR_ICACHEXIPSD_NORMAL << MXC_F_PWRSEQ_MEM_PWR_ICACHEXIPSD_POS) 
#define MXC_V_PWRSEQ_MEM_PWR_ICACHEXIPSD_SHUTDOWN      ((uint32_t)0x1UL) 
#define MXC_S_PWRSEQ_MEM_PWR_ICACHEXIPSD_SHUTDOWN      (MXC_V_PWRSEQ_MEM_PWR_ICACHEXIPSD_SHUTDOWN << MXC_F_PWRSEQ_MEM_PWR_ICACHEXIPSD_POS) 
#define MXC_F_PWRSEQ_MEM_PWR_SCACHESD_POS              9 
#define MXC_F_PWRSEQ_MEM_PWR_SCACHESD                  ((uint32_t)(0x1UL << MXC_F_PWRSEQ_MEM_PWR_SCACHESD_POS)) 
#define MXC_V_PWRSEQ_MEM_PWR_SCACHESD_NORMAL           ((uint32_t)0x0UL) 
#define MXC_S_PWRSEQ_MEM_PWR_SCACHESD_NORMAL           (MXC_V_PWRSEQ_MEM_PWR_SCACHESD_NORMAL << MXC_F_PWRSEQ_MEM_PWR_SCACHESD_POS) 
#define MXC_V_PWRSEQ_MEM_PWR_SCACHESD_SHUTDOWN         ((uint32_t)0x1UL) 
#define MXC_S_PWRSEQ_MEM_PWR_SCACHESD_SHUTDOWN         (MXC_V_PWRSEQ_MEM_PWR_SCACHESD_SHUTDOWN << MXC_F_PWRSEQ_MEM_PWR_SCACHESD_POS) 
#define MXC_F_PWRSEQ_MEM_PWR_CRYPTOSD_POS              10 
#define MXC_F_PWRSEQ_MEM_PWR_CRYPTOSD                  ((uint32_t)(0x1UL << MXC_F_PWRSEQ_MEM_PWR_CRYPTOSD_POS)) 
#define MXC_V_PWRSEQ_MEM_PWR_CRYPTOSD_NORMAL           ((uint32_t)0x0UL) 
#define MXC_S_PWRSEQ_MEM_PWR_CRYPTOSD_NORMAL           (MXC_V_PWRSEQ_MEM_PWR_CRYPTOSD_NORMAL << MXC_F_PWRSEQ_MEM_PWR_CRYPTOSD_POS) 
#define MXC_V_PWRSEQ_MEM_PWR_CRYPTOSD_SHUTDOWN         ((uint32_t)0x1UL) 
#define MXC_S_PWRSEQ_MEM_PWR_CRYPTOSD_SHUTDOWN         (MXC_V_PWRSEQ_MEM_PWR_CRYPTOSD_SHUTDOWN << MXC_F_PWRSEQ_MEM_PWR_CRYPTOSD_POS) 
#define MXC_F_PWRSEQ_MEM_PWR_USBFIFOSD_POS             11 
#define MXC_F_PWRSEQ_MEM_PWR_USBFIFOSD                 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_MEM_PWR_USBFIFOSD_POS)) 
#define MXC_V_PWRSEQ_MEM_PWR_USBFIFOSD_NORMAL          ((uint32_t)0x0UL) 
#define MXC_S_PWRSEQ_MEM_PWR_USBFIFOSD_NORMAL          (MXC_V_PWRSEQ_MEM_PWR_USBFIFOSD_NORMAL << MXC_F_PWRSEQ_MEM_PWR_USBFIFOSD_POS) 
#define MXC_V_PWRSEQ_MEM_PWR_USBFIFOSD_SHUTDOWN        ((uint32_t)0x1UL) 
#define MXC_S_PWRSEQ_MEM_PWR_USBFIFOSD_SHUTDOWN        (MXC_V_PWRSEQ_MEM_PWR_USBFIFOSD_SHUTDOWN << MXC_F_PWRSEQ_MEM_PWR_USBFIFOSD_POS) 
#define MXC_F_PWRSEQ_MEM_PWR_ROMSD_POS                 12 
#define MXC_F_PWRSEQ_MEM_PWR_ROMSD                     ((uint32_t)(0x1UL << MXC_F_PWRSEQ_MEM_PWR_ROMSD_POS)) 
#define MXC_V_PWRSEQ_MEM_PWR_ROMSD_NORMAL              ((uint32_t)0x0UL) 
#define MXC_S_PWRSEQ_MEM_PWR_ROMSD_NORMAL              (MXC_V_PWRSEQ_MEM_PWR_ROMSD_NORMAL << MXC_F_PWRSEQ_MEM_PWR_ROMSD_POS) 
#define MXC_V_PWRSEQ_MEM_PWR_ROMSD_SHUTDOWN            ((uint32_t)0x1UL) 
#define MXC_S_PWRSEQ_MEM_PWR_ROMSD_SHUTDOWN            (MXC_V_PWRSEQ_MEM_PWR_ROMSD_SHUTDOWN << MXC_F_PWRSEQ_MEM_PWR_ROMSD_POS) 
#ifdef __cplusplus
}
#endif
 
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32650_INCLUDE_PWRSEQ_REGS_H_