sdma_regs.h

 
/******************************************************************************
 *
 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 
 * Analog Devices, Inc.),
 * Copyright (C) 2023-2024 Analog Devices, Inc.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 ******************************************************************************/
 
#ifndef _SDMA_REGS_H_
#define _SDMA_REGS_H_
 
/* **** Includes **** */
#include <stdint.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
#if defined (__ICCARM__)
  #pragma system_include
#endif
 
#if defined (__CC_ARM)
  #pragma anon_unions
#endif
/*
    If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I  volatile const
#endif
#ifndef __O
#define __O  volatile
#endif
#ifndef __R
#define __R  volatile const
#endif
 
/* **** Definitions **** */
 
typedef struct {
    __I  uint32_t ip;                   
    __I  uint32_t sp;                   
    __I  uint32_t dp0;                  
    __I  uint32_t dp1;                  
    __I  uint32_t bp;                   
    __I  uint32_t offs;                 
    __I  uint32_t lc0;                  
    __I  uint32_t lc1;                  
    __I  uint32_t a0;                   
    __I  uint32_t a1;                   
    __I  uint32_t a2;                   
    __I  uint32_t a3;                   
    __I  uint32_t wdcn;                 
    __R  uint32_t rsv_0x34_0x7f[19];
    __IO uint32_t int_mux_ctrl0;        
    __IO uint32_t int_mux_ctrl1;        
    __IO uint32_t int_mux_ctrl2;        
    __IO uint32_t int_mux_ctrl3;        
    __IO uint32_t ip_addr;              
    __IO uint32_t ctrl;                 
    __R  uint32_t rsv_0x98_0x9f[2];
    __IO uint32_t int_in_ctrl;          
    __IO uint32_t int_in_flag;          
    __IO uint32_t int_in_ie;            
    __R  uint32_t rsv_0xac;
    __IO uint32_t irq_flag;             
    __IO uint32_t irq_ie;               
} mxc_sdma_regs_t;
 
/* Register offsets for module SDMA */
 #define MXC_R_SDMA_IP                      ((uint32_t)0x00000000UL) 
 #define MXC_R_SDMA_SP                      ((uint32_t)0x00000004UL) 
 #define MXC_R_SDMA_DP0                     ((uint32_t)0x00000008UL) 
 #define MXC_R_SDMA_DP1                     ((uint32_t)0x0000000CUL) 
 #define MXC_R_SDMA_BP                      ((uint32_t)0x00000010UL) 
 #define MXC_R_SDMA_OFFS                    ((uint32_t)0x00000014UL) 
 #define MXC_R_SDMA_LC0                     ((uint32_t)0x00000018UL) 
 #define MXC_R_SDMA_LC1                     ((uint32_t)0x0000001CUL) 
 #define MXC_R_SDMA_A0                      ((uint32_t)0x00000020UL) 
 #define MXC_R_SDMA_A1                      ((uint32_t)0x00000024UL) 
 #define MXC_R_SDMA_A2                      ((uint32_t)0x00000028UL) 
 #define MXC_R_SDMA_A3                      ((uint32_t)0x0000002CUL) 
 #define MXC_R_SDMA_WDCN                    ((uint32_t)0x00000030UL) 
 #define MXC_R_SDMA_INT_MUX_CTRL0           ((uint32_t)0x00000080UL) 
 #define MXC_R_SDMA_INT_MUX_CTRL1           ((uint32_t)0x00000084UL) 
 #define MXC_R_SDMA_INT_MUX_CTRL2           ((uint32_t)0x00000088UL) 
 #define MXC_R_SDMA_INT_MUX_CTRL3           ((uint32_t)0x0000008CUL) 
 #define MXC_R_SDMA_IP_ADDR                 ((uint32_t)0x00000090UL) 
 #define MXC_R_SDMA_CTRL                    ((uint32_t)0x00000094UL) 
 #define MXC_R_SDMA_INT_IN_CTRL             ((uint32_t)0x000000A0UL) 
 #define MXC_R_SDMA_INT_IN_FLAG             ((uint32_t)0x000000A4UL) 
 #define MXC_R_SDMA_INT_IN_IE               ((uint32_t)0x000000A8UL) 
 #define MXC_R_SDMA_IRQ_FLAG                ((uint32_t)0x000000B0UL) 
 #define MXC_R_SDMA_IRQ_IE                  ((uint32_t)0x000000B4UL) 
 #define MXC_F_SDMA_INT_MUX_CTRL0_INTSEL16_POS          0 
 #define MXC_F_SDMA_INT_MUX_CTRL0_INTSEL16              ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL0_INTSEL16_POS)) 
 #define MXC_F_SDMA_INT_MUX_CTRL0_INTSEL17_POS          8 
 #define MXC_F_SDMA_INT_MUX_CTRL0_INTSEL17              ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL0_INTSEL17_POS)) 
 #define MXC_F_SDMA_INT_MUX_CTRL0_INTSEL18_POS          16 
 #define MXC_F_SDMA_INT_MUX_CTRL0_INTSEL18              ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL0_INTSEL18_POS)) 
 #define MXC_F_SDMA_INT_MUX_CTRL0_INTSEL19_POS          24 
 #define MXC_F_SDMA_INT_MUX_CTRL0_INTSEL19              ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL0_INTSEL19_POS)) 
 #define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL20_POS          0 
 #define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL20              ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL1_INTSEL20_POS)) 
 #define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL21_POS          8 
 #define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL21              ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL1_INTSEL21_POS)) 
 #define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL22_POS          16 
 #define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL22              ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL1_INTSEL22_POS)) 
 #define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL23_POS          24 
 #define MXC_F_SDMA_INT_MUX_CTRL1_INTSEL23              ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL1_INTSEL23_POS)) 
 #define MXC_F_SDMA_INT_MUX_CTRL2_INTSEL24_POS          0 
 #define MXC_F_SDMA_INT_MUX_CTRL2_INTSEL24              ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL2_INTSEL24_POS)) 
 #define MXC_F_SDMA_INT_MUX_CTRL2_INTSEL25_POS          8 
 #define MXC_F_SDMA_INT_MUX_CTRL2_INTSEL25              ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL2_INTSEL25_POS)) 
 #define MXC_F_SDMA_INT_MUX_CTRL2_INTSEL26_POS          16 
 #define MXC_F_SDMA_INT_MUX_CTRL2_INTSEL26              ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL2_INTSEL26_POS)) 
 #define MXC_F_SDMA_INT_MUX_CTRL2_INTSEL27_POS          24 
 #define MXC_F_SDMA_INT_MUX_CTRL2_INTSEL27              ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL2_INTSEL27_POS)) 
 #define MXC_F_SDMA_INT_MUX_CTRL3_INTSEL28_POS          0 
 #define MXC_F_SDMA_INT_MUX_CTRL3_INTSEL28              ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL3_INTSEL28_POS)) 
 #define MXC_F_SDMA_INT_MUX_CTRL3_INTSEL29_POS          8 
 #define MXC_F_SDMA_INT_MUX_CTRL3_INTSEL29              ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL3_INTSEL29_POS)) 
 #define MXC_F_SDMA_INT_MUX_CTRL3_INTSEL30_POS          16 
 #define MXC_F_SDMA_INT_MUX_CTRL3_INTSEL30              ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL3_INTSEL30_POS)) 
 #define MXC_F_SDMA_INT_MUX_CTRL3_INTSEL31_POS          24 
 #define MXC_F_SDMA_INT_MUX_CTRL3_INTSEL31              ((uint32_t)(0xFFUL << MXC_F_SDMA_INT_MUX_CTRL3_INTSEL31_POS)) 
 #define MXC_F_SDMA_IP_ADDR_START_IP_ADDR_POS           0 
 #define MXC_F_SDMA_IP_ADDR_START_IP_ADDR               ((uint32_t)(0xFFFFFFFFUL << MXC_F_SDMA_IP_ADDR_START_IP_ADDR_POS)) 
 #define MXC_F_SDMA_CTRL_EN_POS                         0 
 #define MXC_F_SDMA_CTRL_EN                             ((uint32_t)(0x1UL << MXC_F_SDMA_CTRL_EN_POS)) 
 #define MXC_V_SDMA_CTRL_EN_DIS                         ((uint32_t)0x0UL) 
 #define MXC_S_SDMA_CTRL_EN_DIS                         (MXC_V_SDMA_CTRL_EN_DIS << MXC_F_SDMA_CTRL_EN_POS) 
 #define MXC_V_SDMA_CTRL_EN_EN                          ((uint32_t)0x1UL) 
 #define MXC_S_SDMA_CTRL_EN_EN                          (MXC_V_SDMA_CTRL_EN_EN << MXC_F_SDMA_CTRL_EN_POS) 
 #define MXC_F_SDMA_INT_IN_CTRL_INTSET_POS              0 
 #define MXC_F_SDMA_INT_IN_CTRL_INTSET                  ((uint32_t)(0x1UL << MXC_F_SDMA_INT_IN_CTRL_INTSET_POS)) 
 #define MXC_V_SDMA_INT_IN_CTRL_INTSET_DIS              ((uint32_t)0x0UL) 
 #define MXC_S_SDMA_INT_IN_CTRL_INTSET_DIS              (MXC_V_SDMA_INT_IN_CTRL_INTSET_DIS << MXC_F_SDMA_INT_IN_CTRL_INTSET_POS) 
 #define MXC_V_SDMA_INT_IN_CTRL_INTSET_SET              ((uint32_t)0x1UL) 
 #define MXC_S_SDMA_INT_IN_CTRL_INTSET_SET              (MXC_V_SDMA_INT_IN_CTRL_INTSET_SET << MXC_F_SDMA_INT_IN_CTRL_INTSET_POS) 
 #define MXC_F_SDMA_INT_IN_FLAG_INTFLAG_POS             0 
 #define MXC_F_SDMA_INT_IN_FLAG_INTFLAG                 ((uint32_t)(0x1UL << MXC_F_SDMA_INT_IN_FLAG_INTFLAG_POS)) 
 #define MXC_V_SDMA_INT_IN_FLAG_INTFLAG_NO_EFF          ((uint32_t)0x0UL) 
 #define MXC_S_SDMA_INT_IN_FLAG_INTFLAG_NO_EFF          (MXC_V_SDMA_INT_IN_FLAG_INTFLAG_NO_EFF << MXC_F_SDMA_INT_IN_FLAG_INTFLAG_POS) 
 #define MXC_V_SDMA_INT_IN_FLAG_INTFLAG_CLEAR           ((uint32_t)0x1UL) 
 #define MXC_S_SDMA_INT_IN_FLAG_INTFLAG_CLEAR           (MXC_V_SDMA_INT_IN_FLAG_INTFLAG_CLEAR << MXC_F_SDMA_INT_IN_FLAG_INTFLAG_POS) 
 #define MXC_F_SDMA_INT_IN_IE_INT_IN_EN_POS             0 
 #define MXC_F_SDMA_INT_IN_IE_INT_IN_EN                 ((uint32_t)(0x1UL << MXC_F_SDMA_INT_IN_IE_INT_IN_EN_POS)) 
 #define MXC_F_SDMA_IRQ_FLAG_IRQ_FLAG_POS               0 
 #define MXC_F_SDMA_IRQ_FLAG_IRQ_FLAG                   ((uint32_t)(0x1UL << MXC_F_SDMA_IRQ_FLAG_IRQ_FLAG_POS)) 
 #define MXC_F_SDMA_IRQ_IE_IRQ_EN_POS                   0 
 #define MXC_F_SDMA_IRQ_IE_IRQ_EN                       ((uint32_t)(0x1UL << MXC_F_SDMA_IRQ_IE_IRQ_EN_POS)) 
#ifdef __cplusplus
}
#endif
 
#endif /* _SDMA_REGS_H_ */