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#define | MXC_R_ADC_CTRL ((uint32_t)0x00000000UL) |
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#define | MXC_R_ADC_STATUS ((uint32_t)0x00000004UL) |
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#define | MXC_R_ADC_DATA ((uint32_t)0x00000008UL) |
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#define | MXC_R_ADC_INTR ((uint32_t)0x0000000CUL) |
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#define | MXC_R_ADC_LIMIT ((uint32_t)0x00000010UL) |
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#define | MXC_F_ADC_CTRL_START_POS 0 |
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#define | MXC_F_ADC_CTRL_START ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_START_POS)) |
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#define | MXC_F_ADC_CTRL_PWR_POS 1 |
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#define | MXC_F_ADC_CTRL_PWR ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_PWR_POS)) |
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#define | MXC_F_ADC_CTRL_REFBUF_PWR_POS 3 |
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#define | MXC_F_ADC_CTRL_REFBUF_PWR ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_REFBUF_PWR_POS)) |
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#define | MXC_F_ADC_CTRL_REF_SEL_POS 4 |
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#define | MXC_F_ADC_CTRL_REF_SEL ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_REF_SEL_POS)) |
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#define | MXC_F_ADC_CTRL_REF_SCALE_POS 8 |
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#define | MXC_F_ADC_CTRL_REF_SCALE ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_REF_SCALE_POS)) |
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#define | MXC_F_ADC_CTRL_SCALE_POS 9 |
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#define | MXC_F_ADC_CTRL_SCALE ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_SCALE_POS)) |
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#define | MXC_F_ADC_CTRL_CLK_EN_POS 11 |
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#define | MXC_F_ADC_CTRL_CLK_EN ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_CLK_EN_POS)) |
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#define | MXC_F_ADC_CTRL_CH_SEL_POS 12 |
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#define | MXC_F_ADC_CTRL_CH_SEL ((uint32_t)(0x1FUL << MXC_F_ADC_CTRL_CH_SEL_POS)) |
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#define | MXC_V_ADC_CTRL_CH_SEL_AIN0 ((uint32_t)0x0UL) |
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#define | MXC_S_ADC_CTRL_CH_SEL_AIN0 (MXC_V_ADC_CTRL_CH_SEL_AIN0 << MXC_F_ADC_CTRL_CH_SEL_POS) |
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#define | MXC_V_ADC_CTRL_CH_SEL_AIN1 ((uint32_t)0x1UL) |
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#define | MXC_S_ADC_CTRL_CH_SEL_AIN1 (MXC_V_ADC_CTRL_CH_SEL_AIN1 << MXC_F_ADC_CTRL_CH_SEL_POS) |
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#define | MXC_V_ADC_CTRL_CH_SEL_AIN2 ((uint32_t)0x2UL) |
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#define | MXC_S_ADC_CTRL_CH_SEL_AIN2 (MXC_V_ADC_CTRL_CH_SEL_AIN2 << MXC_F_ADC_CTRL_CH_SEL_POS) |
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#define | MXC_V_ADC_CTRL_CH_SEL_AIN3 ((uint32_t)0x3UL) |
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#define | MXC_S_ADC_CTRL_CH_SEL_AIN3 (MXC_V_ADC_CTRL_CH_SEL_AIN3 << MXC_F_ADC_CTRL_CH_SEL_POS) |
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#define | MXC_V_ADC_CTRL_CH_SEL_AIN4 ((uint32_t)0x4UL) |
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#define | MXC_S_ADC_CTRL_CH_SEL_AIN4 (MXC_V_ADC_CTRL_CH_SEL_AIN4 << MXC_F_ADC_CTRL_CH_SEL_POS) |
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#define | MXC_V_ADC_CTRL_CH_SEL_AIN5 ((uint32_t)0x5UL) |
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#define | MXC_S_ADC_CTRL_CH_SEL_AIN5 (MXC_V_ADC_CTRL_CH_SEL_AIN5 << MXC_F_ADC_CTRL_CH_SEL_POS) |
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#define | MXC_V_ADC_CTRL_CH_SEL_AIN6 ((uint32_t)0x6UL) |
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#define | MXC_S_ADC_CTRL_CH_SEL_AIN6 (MXC_V_ADC_CTRL_CH_SEL_AIN6 << MXC_F_ADC_CTRL_CH_SEL_POS) |
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#define | MXC_V_ADC_CTRL_CH_SEL_AIN7 ((uint32_t)0x7UL) |
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#define | MXC_S_ADC_CTRL_CH_SEL_AIN7 (MXC_V_ADC_CTRL_CH_SEL_AIN7 << MXC_F_ADC_CTRL_CH_SEL_POS) |
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#define | MXC_V_ADC_CTRL_CH_SEL_VCOREA ((uint32_t)0x8UL) |
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#define | MXC_S_ADC_CTRL_CH_SEL_VCOREA (MXC_V_ADC_CTRL_CH_SEL_VCOREA << MXC_F_ADC_CTRL_CH_SEL_POS) |
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#define | MXC_V_ADC_CTRL_CH_SEL_VCOREB ((uint32_t)0x9UL) |
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#define | MXC_S_ADC_CTRL_CH_SEL_VCOREB (MXC_V_ADC_CTRL_CH_SEL_VCOREB << MXC_F_ADC_CTRL_CH_SEL_POS) |
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#define | MXC_V_ADC_CTRL_CH_SEL_VRXOUT ((uint32_t)0xAUL) |
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#define | MXC_S_ADC_CTRL_CH_SEL_VRXOUT (MXC_V_ADC_CTRL_CH_SEL_VRXOUT << MXC_F_ADC_CTRL_CH_SEL_POS) |
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#define | MXC_V_ADC_CTRL_CH_SEL_VTXOUT ((uint32_t)0xBUL) |
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#define | MXC_S_ADC_CTRL_CH_SEL_VTXOUT (MXC_V_ADC_CTRL_CH_SEL_VTXOUT << MXC_F_ADC_CTRL_CH_SEL_POS) |
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#define | MXC_V_ADC_CTRL_CH_SEL_VDDA ((uint32_t)0xCUL) |
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#define | MXC_S_ADC_CTRL_CH_SEL_VDDA (MXC_V_ADC_CTRL_CH_SEL_VDDA << MXC_F_ADC_CTRL_CH_SEL_POS) |
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#define | MXC_V_ADC_CTRL_CH_SEL_VDDB ((uint32_t)0xDUL) |
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#define | MXC_S_ADC_CTRL_CH_SEL_VDDB (MXC_V_ADC_CTRL_CH_SEL_VDDB << MXC_F_ADC_CTRL_CH_SEL_POS) |
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#define | MXC_V_ADC_CTRL_CH_SEL_VDDIO ((uint32_t)0xEUL) |
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#define | MXC_S_ADC_CTRL_CH_SEL_VDDIO (MXC_V_ADC_CTRL_CH_SEL_VDDIO << MXC_F_ADC_CTRL_CH_SEL_POS) |
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#define | MXC_V_ADC_CTRL_CH_SEL_VDDIOH ((uint32_t)0xFUL) |
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#define | MXC_S_ADC_CTRL_CH_SEL_VDDIOH (MXC_V_ADC_CTRL_CH_SEL_VDDIOH << MXC_F_ADC_CTRL_CH_SEL_POS) |
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#define | MXC_V_ADC_CTRL_CH_SEL_VREGI ((uint32_t)0x10UL) |
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#define | MXC_S_ADC_CTRL_CH_SEL_VREGI (MXC_V_ADC_CTRL_CH_SEL_VREGI << MXC_F_ADC_CTRL_CH_SEL_POS) |
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#define | MXC_F_ADC_CTRL_ADC_DIVSEL_POS 17 |
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#define | MXC_F_ADC_CTRL_ADC_DIVSEL ((uint32_t)(0x3UL << MXC_F_ADC_CTRL_ADC_DIVSEL_POS)) |
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#define | MXC_V_ADC_CTRL_ADC_DIVSEL_DIV1 ((uint32_t)0x0UL) |
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#define | MXC_S_ADC_CTRL_ADC_DIVSEL_DIV1 (MXC_V_ADC_CTRL_ADC_DIVSEL_DIV1 << MXC_F_ADC_CTRL_ADC_DIVSEL_POS) |
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#define | MXC_V_ADC_CTRL_ADC_DIVSEL_DIV2 ((uint32_t)0x1UL) |
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#define | MXC_S_ADC_CTRL_ADC_DIVSEL_DIV2 (MXC_V_ADC_CTRL_ADC_DIVSEL_DIV2 << MXC_F_ADC_CTRL_ADC_DIVSEL_POS) |
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#define | MXC_V_ADC_CTRL_ADC_DIVSEL_DIV3 ((uint32_t)0x2UL) |
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#define | MXC_S_ADC_CTRL_ADC_DIVSEL_DIV3 (MXC_V_ADC_CTRL_ADC_DIVSEL_DIV3 << MXC_F_ADC_CTRL_ADC_DIVSEL_POS) |
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#define | MXC_V_ADC_CTRL_ADC_DIVSEL_DIV4 ((uint32_t)0x3UL) |
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#define | MXC_S_ADC_CTRL_ADC_DIVSEL_DIV4 (MXC_V_ADC_CTRL_ADC_DIVSEL_DIV4 << MXC_F_ADC_CTRL_ADC_DIVSEL_POS) |
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#define | MXC_F_ADC_CTRL_DATA_ALIGN_POS 20 |
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#define | MXC_F_ADC_CTRL_DATA_ALIGN ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_DATA_ALIGN_POS)) |
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#define | MXC_F_ADC_STATUS_ACTIVE_POS 0 |
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#define | MXC_F_ADC_STATUS_ACTIVE ((uint32_t)(0x1UL << MXC_F_ADC_STATUS_ACTIVE_POS)) |
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#define | MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE_POS 2 |
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#define | MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE ((uint32_t)(0x1UL << MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE_POS)) |
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#define | MXC_F_ADC_STATUS_OVERFLOW_POS 3 |
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#define | MXC_F_ADC_STATUS_OVERFLOW ((uint32_t)(0x1UL << MXC_F_ADC_STATUS_OVERFLOW_POS)) |
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#define | MXC_F_ADC_DATA_ADC_DATA_POS 0 |
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#define | MXC_F_ADC_DATA_ADC_DATA ((uint32_t)(0xFFFFUL << MXC_F_ADC_DATA_ADC_DATA_POS)) |
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#define | MXC_F_ADC_INTR_DONE_IE_POS 0 |
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#define | MXC_F_ADC_INTR_DONE_IE ((uint32_t)(0x1UL << MXC_F_ADC_INTR_DONE_IE_POS)) |
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#define | MXC_F_ADC_INTR_REF_READY_IE_POS 1 |
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#define | MXC_F_ADC_INTR_REF_READY_IE ((uint32_t)(0x1UL << MXC_F_ADC_INTR_REF_READY_IE_POS)) |
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#define | MXC_F_ADC_INTR_HI_LIMIT_IE_POS 2 |
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#define | MXC_F_ADC_INTR_HI_LIMIT_IE ((uint32_t)(0x1UL << MXC_F_ADC_INTR_HI_LIMIT_IE_POS)) |
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#define | MXC_F_ADC_INTR_LO_LIMIT_IE_POS 3 |
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#define | MXC_F_ADC_INTR_LO_LIMIT_IE ((uint32_t)(0x1UL << MXC_F_ADC_INTR_LO_LIMIT_IE_POS)) |
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#define | MXC_F_ADC_INTR_OVERFLOW_IE_POS 4 |
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#define | MXC_F_ADC_INTR_OVERFLOW_IE ((uint32_t)(0x1UL << MXC_F_ADC_INTR_OVERFLOW_IE_POS)) |
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#define | MXC_F_ADC_INTR_DONE_IF_POS 16 |
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#define | MXC_F_ADC_INTR_DONE_IF ((uint32_t)(0x1UL << MXC_F_ADC_INTR_DONE_IF_POS)) |
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#define | MXC_F_ADC_INTR_REF_READY_IF_POS 17 |
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#define | MXC_F_ADC_INTR_REF_READY_IF ((uint32_t)(0x1UL << MXC_F_ADC_INTR_REF_READY_IF_POS)) |
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#define | MXC_F_ADC_INTR_HI_LIMIT_IF_POS 18 |
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#define | MXC_F_ADC_INTR_HI_LIMIT_IF ((uint32_t)(0x1UL << MXC_F_ADC_INTR_HI_LIMIT_IF_POS)) |
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#define | MXC_F_ADC_INTR_LO_LIMIT_IF_POS 19 |
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#define | MXC_F_ADC_INTR_LO_LIMIT_IF ((uint32_t)(0x1UL << MXC_F_ADC_INTR_LO_LIMIT_IF_POS)) |
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#define | MXC_F_ADC_INTR_OVERFLOW_IF_POS 20 |
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#define | MXC_F_ADC_INTR_OVERFLOW_IF ((uint32_t)(0x1UL << MXC_F_ADC_INTR_OVERFLOW_IF_POS)) |
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#define | MXC_F_ADC_INTR_PENDING_POS 22 |
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#define | MXC_F_ADC_INTR_PENDING ((uint32_t)(0x1UL << MXC_F_ADC_INTR_PENDING_POS)) |
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#define | MXC_F_ADC_LIMIT_CH_LO_LIMIT_POS 0 |
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#define | MXC_F_ADC_LIMIT_CH_LO_LIMIT ((uint32_t)(0x3FFUL << MXC_F_ADC_LIMIT_CH_LO_LIMIT_POS)) |
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#define | MXC_F_ADC_LIMIT_CH_HI_LIMIT_POS 12 |
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#define | MXC_F_ADC_LIMIT_CH_HI_LIMIT ((uint32_t)(0x3FFUL << MXC_F_ADC_LIMIT_CH_HI_LIMIT_POS)) |
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#define | MXC_F_ADC_LIMIT_CH_SEL_POS 24 |
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#define | MXC_F_ADC_LIMIT_CH_SEL ((uint32_t)(0x1FUL << MXC_F_ADC_LIMIT_CH_SEL_POS)) |
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#define | MXC_F_ADC_LIMIT_CH_LO_LIMIT_EN_POS 29 |
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#define | MXC_F_ADC_LIMIT_CH_LO_LIMIT_EN ((uint32_t)(0x1UL << MXC_F_ADC_LIMIT_CH_LO_LIMIT_EN_POS)) |
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#define | MXC_F_ADC_LIMIT_CH_HI_LIMIT_EN_POS 30 |
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#define | MXC_F_ADC_LIMIT_CH_HI_LIMIT_EN ((uint32_t)(0x1UL << MXC_F_ADC_LIMIT_CH_HI_LIMIT_EN_POS)) |
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