dma_regs.h

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/******************************************************************************
 *
 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 
 * Analog Devices, Inc.),
 * Copyright (C) 2023-2024 Analog Devices, Inc.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 ******************************************************************************/
 
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_DMA_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_DMA_REGS_H_
 
/* **** Includes **** */
#include <stdint.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
#if defined (__ICCARM__)
  #pragma system_include
#endif
 
#if defined (__CC_ARM)
  #pragma anon_unions
#endif
/*
    If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I  volatile const
#endif
#ifndef __O
#define __O  volatile
#endif
#ifndef __R
#define __R  volatile const
#endif
 
/* **** Definitions **** */
 
typedef struct {
    __IO uint32_t ctrl;                 
    __IO uint32_t status;               
    __IO uint32_t src;                  
    __IO uint32_t dst;                  
    __IO uint32_t cnt;                  
    __IO uint32_t srcrld;               
    __IO uint32_t dstrld;               
    __IO uint32_t cntrld;               
} mxc_dma_ch_regs_t;
 
typedef struct {
    __IO uint32_t inten;                
    __I  uint32_t intfl;                
    __R  uint32_t rsv_0x8_0xff[62];
    __IO mxc_dma_ch_regs_t    ch[4];    
} mxc_dma_regs_t;
 
/* Register offsets for module DMA */
#define MXC_R_DMA_CTRL                     ((uint32_t)0x00000000UL) 
#define MXC_R_DMA_STATUS                   ((uint32_t)0x00000004UL) 
#define MXC_R_DMA_SRC                      ((uint32_t)0x00000008UL) 
#define MXC_R_DMA_DST                      ((uint32_t)0x0000000CUL) 
#define MXC_R_DMA_CNT                      ((uint32_t)0x00000010UL) 
#define MXC_R_DMA_SRCRLD                   ((uint32_t)0x00000014UL) 
#define MXC_R_DMA_DSTRLD                   ((uint32_t)0x00000018UL) 
#define MXC_R_DMA_CNTRLD                   ((uint32_t)0x0000001CUL) 
#define MXC_R_DMA_INTEN                    ((uint32_t)0x00000000UL) 
#define MXC_R_DMA_INTFL                    ((uint32_t)0x00000004UL) 
#define MXC_R_DMA_CH                       ((uint32_t)0x00000100UL) 
#define MXC_F_DMA_INTEN_CH0_POS                        0 
#define MXC_F_DMA_INTEN_CH0                            ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH0_POS)) 
#define MXC_F_DMA_INTEN_CH1_POS                        1 
#define MXC_F_DMA_INTEN_CH1                            ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH1_POS)) 
#define MXC_F_DMA_INTEN_CH2_POS                        2 
#define MXC_F_DMA_INTEN_CH2                            ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH2_POS)) 
#define MXC_F_DMA_INTEN_CH3_POS                        3 
#define MXC_F_DMA_INTEN_CH3                            ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH3_POS)) 
#define MXC_F_DMA_INTFL_CH0_POS                        0 
#define MXC_F_DMA_INTFL_CH0                            ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH0_POS)) 
#define MXC_F_DMA_INTFL_CH1_POS                        1 
#define MXC_F_DMA_INTFL_CH1                            ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH1_POS)) 
#define MXC_F_DMA_INTFL_CH2_POS                        2 
#define MXC_F_DMA_INTFL_CH2                            ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH2_POS)) 
#define MXC_F_DMA_INTFL_CH3_POS                        3 
#define MXC_F_DMA_INTFL_CH3                            ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH3_POS)) 
#define MXC_F_DMA_CTRL_EN_POS                          0 
#define MXC_F_DMA_CTRL_EN                              ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_EN_POS)) 
#define MXC_F_DMA_CTRL_RLDEN_POS                       1 
#define MXC_F_DMA_CTRL_RLDEN                           ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_RLDEN_POS)) 
#define MXC_F_DMA_CTRL_PRI_POS                         2 
#define MXC_F_DMA_CTRL_PRI                             ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_PRI_POS)) 
#define MXC_V_DMA_CTRL_PRI_HIGH                        ((uint32_t)0x0UL) 
#define MXC_S_DMA_CTRL_PRI_HIGH                        (MXC_V_DMA_CTRL_PRI_HIGH << MXC_F_DMA_CTRL_PRI_POS) 
#define MXC_V_DMA_CTRL_PRI_MEDHIGH                     ((uint32_t)0x1UL) 
#define MXC_S_DMA_CTRL_PRI_MEDHIGH                     (MXC_V_DMA_CTRL_PRI_MEDHIGH << MXC_F_DMA_CTRL_PRI_POS) 
#define MXC_V_DMA_CTRL_PRI_MEDLOW                      ((uint32_t)0x2UL) 
#define MXC_S_DMA_CTRL_PRI_MEDLOW                      (MXC_V_DMA_CTRL_PRI_MEDLOW << MXC_F_DMA_CTRL_PRI_POS) 
#define MXC_V_DMA_CTRL_PRI_LOW                         ((uint32_t)0x3UL) 
#define MXC_S_DMA_CTRL_PRI_LOW                         (MXC_V_DMA_CTRL_PRI_LOW << MXC_F_DMA_CTRL_PRI_POS) 
#define MXC_F_DMA_CTRL_REQUEST_POS                     4 
#define MXC_F_DMA_CTRL_REQUEST                         ((uint32_t)(0x3FUL << MXC_F_DMA_CTRL_REQUEST_POS)) 
#define MXC_V_DMA_CTRL_REQUEST_MEMTOMEM                ((uint32_t)0x0UL) 
#define MXC_S_DMA_CTRL_REQUEST_MEMTOMEM                (MXC_V_DMA_CTRL_REQUEST_MEMTOMEM << MXC_F_DMA_CTRL_REQUEST_POS) 
#define MXC_V_DMA_CTRL_REQUEST_SPI1RX                  ((uint32_t)0x1UL) 
#define MXC_S_DMA_CTRL_REQUEST_SPI1RX                  (MXC_V_DMA_CTRL_REQUEST_SPI1RX << MXC_F_DMA_CTRL_REQUEST_POS) 
#define MXC_V_DMA_CTRL_REQUEST_UART0RX                 ((uint32_t)0x4UL) 
#define MXC_S_DMA_CTRL_REQUEST_UART0RX                 (MXC_V_DMA_CTRL_REQUEST_UART0RX << MXC_F_DMA_CTRL_REQUEST_POS) 
#define MXC_V_DMA_CTRL_REQUEST_UART1RX                 ((uint32_t)0x5UL) 
#define MXC_S_DMA_CTRL_REQUEST_UART1RX                 (MXC_V_DMA_CTRL_REQUEST_UART1RX << MXC_F_DMA_CTRL_REQUEST_POS) 
#define MXC_V_DMA_CTRL_REQUEST_I2C0RX                  ((uint32_t)0x7UL) 
#define MXC_S_DMA_CTRL_REQUEST_I2C0RX                  (MXC_V_DMA_CTRL_REQUEST_I2C0RX << MXC_F_DMA_CTRL_REQUEST_POS) 
#define MXC_V_DMA_CTRL_REQUEST_I2C1RX                  ((uint32_t)0x8UL) 
#define MXC_S_DMA_CTRL_REQUEST_I2C1RX                  (MXC_V_DMA_CTRL_REQUEST_I2C1RX << MXC_F_DMA_CTRL_REQUEST_POS) 
#define MXC_V_DMA_CTRL_REQUEST_ADC                     ((uint32_t)0x9UL) 
#define MXC_S_DMA_CTRL_REQUEST_ADC                     (MXC_V_DMA_CTRL_REQUEST_ADC << MXC_F_DMA_CTRL_REQUEST_POS) 
#define MXC_V_DMA_CTRL_REQUEST_I2C2RX                  ((uint32_t)0xAUL) 
#define MXC_S_DMA_CTRL_REQUEST_I2C2RX                  (MXC_V_DMA_CTRL_REQUEST_I2C2RX << MXC_F_DMA_CTRL_REQUEST_POS) 
#define MXC_V_DMA_CTRL_REQUEST_UART2RX                 ((uint32_t)0xEUL) 
#define MXC_S_DMA_CTRL_REQUEST_UART2RX                 (MXC_V_DMA_CTRL_REQUEST_UART2RX << MXC_F_DMA_CTRL_REQUEST_POS) 
#define MXC_V_DMA_CTRL_REQUEST_SPI0RX                  ((uint32_t)0xFUL) 
#define MXC_S_DMA_CTRL_REQUEST_SPI0RX                  (MXC_V_DMA_CTRL_REQUEST_SPI0RX << MXC_F_DMA_CTRL_REQUEST_POS) 
#define MXC_V_DMA_CTRL_REQUEST_AESRX                   ((uint32_t)0x10UL) 
#define MXC_S_DMA_CTRL_REQUEST_AESRX                   (MXC_V_DMA_CTRL_REQUEST_AESRX << MXC_F_DMA_CTRL_REQUEST_POS) 
#define MXC_V_DMA_CTRL_REQUEST_UART3RX                 ((uint32_t)0x1CUL) 
#define MXC_S_DMA_CTRL_REQUEST_UART3RX                 (MXC_V_DMA_CTRL_REQUEST_UART3RX << MXC_F_DMA_CTRL_REQUEST_POS) 
#define MXC_V_DMA_CTRL_REQUEST_I2SRX                   ((uint32_t)0x1EUL) 
#define MXC_S_DMA_CTRL_REQUEST_I2SRX                   (MXC_V_DMA_CTRL_REQUEST_I2SRX << MXC_F_DMA_CTRL_REQUEST_POS) 
#define MXC_V_DMA_CTRL_REQUEST_SPI1TX                  ((uint32_t)0x21UL) 
#define MXC_S_DMA_CTRL_REQUEST_SPI1TX                  (MXC_V_DMA_CTRL_REQUEST_SPI1TX << MXC_F_DMA_CTRL_REQUEST_POS) 
#define MXC_V_DMA_CTRL_REQUEST_UART0TX                 ((uint32_t)0x24UL) 
#define MXC_S_DMA_CTRL_REQUEST_UART0TX                 (MXC_V_DMA_CTRL_REQUEST_UART0TX << MXC_F_DMA_CTRL_REQUEST_POS) 
#define MXC_V_DMA_CTRL_REQUEST_UART1TX                 ((uint32_t)0x25UL) 
#define MXC_S_DMA_CTRL_REQUEST_UART1TX                 (MXC_V_DMA_CTRL_REQUEST_UART1TX << MXC_F_DMA_CTRL_REQUEST_POS) 
#define MXC_V_DMA_CTRL_REQUEST_I2C0TX                  ((uint32_t)0x27UL) 
#define MXC_S_DMA_CTRL_REQUEST_I2C0TX                  (MXC_V_DMA_CTRL_REQUEST_I2C0TX << MXC_F_DMA_CTRL_REQUEST_POS) 
#define MXC_V_DMA_CTRL_REQUEST_I2C1TX                  ((uint32_t)0x28UL) 
#define MXC_S_DMA_CTRL_REQUEST_I2C1TX                  (MXC_V_DMA_CTRL_REQUEST_I2C1TX << MXC_F_DMA_CTRL_REQUEST_POS) 
#define MXC_V_DMA_CTRL_REQUEST_I2C2TX                  ((uint32_t)0x2AUL) 
#define MXC_S_DMA_CTRL_REQUEST_I2C2TX                  (MXC_V_DMA_CTRL_REQUEST_I2C2TX << MXC_F_DMA_CTRL_REQUEST_POS) 
#define MXC_V_DMA_CTRL_REQUEST_CRCTX                   ((uint32_t)0x2CUL) 
#define MXC_S_DMA_CTRL_REQUEST_CRCTX                   (MXC_V_DMA_CTRL_REQUEST_CRCTX << MXC_F_DMA_CTRL_REQUEST_POS) 
#define MXC_V_DMA_CTRL_REQUEST_UART2TX                 ((uint32_t)0x2EUL) 
#define MXC_S_DMA_CTRL_REQUEST_UART2TX                 (MXC_V_DMA_CTRL_REQUEST_UART2TX << MXC_F_DMA_CTRL_REQUEST_POS) 
#define MXC_V_DMA_CTRL_REQUEST_SPI0TX                  ((uint32_t)0x2FUL) 
#define MXC_S_DMA_CTRL_REQUEST_SPI0TX                  (MXC_V_DMA_CTRL_REQUEST_SPI0TX << MXC_F_DMA_CTRL_REQUEST_POS) 
#define MXC_V_DMA_CTRL_REQUEST_AESTX                   ((uint32_t)0x30UL) 
#define MXC_S_DMA_CTRL_REQUEST_AESTX                   (MXC_V_DMA_CTRL_REQUEST_AESTX << MXC_F_DMA_CTRL_REQUEST_POS) 
#define MXC_V_DMA_CTRL_REQUEST_UART3TX                 ((uint32_t)0x3CUL) 
#define MXC_S_DMA_CTRL_REQUEST_UART3TX                 (MXC_V_DMA_CTRL_REQUEST_UART3TX << MXC_F_DMA_CTRL_REQUEST_POS) 
#define MXC_V_DMA_CTRL_REQUEST_I2STX                   ((uint32_t)0x3EUL) 
#define MXC_S_DMA_CTRL_REQUEST_I2STX                   (MXC_V_DMA_CTRL_REQUEST_I2STX << MXC_F_DMA_CTRL_REQUEST_POS) 
#define MXC_F_DMA_CTRL_TO_WAIT_POS                     10 
#define MXC_F_DMA_CTRL_TO_WAIT                         ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_TO_WAIT_POS)) 
#define MXC_F_DMA_CTRL_TO_PER_POS                      11 
#define MXC_F_DMA_CTRL_TO_PER                          ((uint32_t)(0x7UL << MXC_F_DMA_CTRL_TO_PER_POS)) 
#define MXC_V_DMA_CTRL_TO_PER_TO4                      ((uint32_t)0x0UL) 
#define MXC_S_DMA_CTRL_TO_PER_TO4                      (MXC_V_DMA_CTRL_TO_PER_TO4 << MXC_F_DMA_CTRL_TO_PER_POS) 
#define MXC_V_DMA_CTRL_TO_PER_TO8                      ((uint32_t)0x1UL) 
#define MXC_S_DMA_CTRL_TO_PER_TO8                      (MXC_V_DMA_CTRL_TO_PER_TO8 << MXC_F_DMA_CTRL_TO_PER_POS) 
#define MXC_V_DMA_CTRL_TO_PER_TO16                     ((uint32_t)0x2UL) 
#define MXC_S_DMA_CTRL_TO_PER_TO16                     (MXC_V_DMA_CTRL_TO_PER_TO16 << MXC_F_DMA_CTRL_TO_PER_POS) 
#define MXC_V_DMA_CTRL_TO_PER_TO32                     ((uint32_t)0x3UL) 
#define MXC_S_DMA_CTRL_TO_PER_TO32                     (MXC_V_DMA_CTRL_TO_PER_TO32 << MXC_F_DMA_CTRL_TO_PER_POS) 
#define MXC_V_DMA_CTRL_TO_PER_TO64                     ((uint32_t)0x4UL) 
#define MXC_S_DMA_CTRL_TO_PER_TO64                     (MXC_V_DMA_CTRL_TO_PER_TO64 << MXC_F_DMA_CTRL_TO_PER_POS) 
#define MXC_V_DMA_CTRL_TO_PER_TO128                    ((uint32_t)0x5UL) 
#define MXC_S_DMA_CTRL_TO_PER_TO128                    (MXC_V_DMA_CTRL_TO_PER_TO128 << MXC_F_DMA_CTRL_TO_PER_POS) 
#define MXC_V_DMA_CTRL_TO_PER_TO256                    ((uint32_t)0x6UL) 
#define MXC_S_DMA_CTRL_TO_PER_TO256                    (MXC_V_DMA_CTRL_TO_PER_TO256 << MXC_F_DMA_CTRL_TO_PER_POS) 
#define MXC_V_DMA_CTRL_TO_PER_TO512                    ((uint32_t)0x7UL) 
#define MXC_S_DMA_CTRL_TO_PER_TO512                    (MXC_V_DMA_CTRL_TO_PER_TO512 << MXC_F_DMA_CTRL_TO_PER_POS) 
#define MXC_F_DMA_CTRL_TO_CLKDIV_POS                   14 
#define MXC_F_DMA_CTRL_TO_CLKDIV                       ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_TO_CLKDIV_POS)) 
#define MXC_V_DMA_CTRL_TO_CLKDIV_DIS                   ((uint32_t)0x0UL) 
#define MXC_S_DMA_CTRL_TO_CLKDIV_DIS                   (MXC_V_DMA_CTRL_TO_CLKDIV_DIS << MXC_F_DMA_CTRL_TO_CLKDIV_POS) 
#define MXC_V_DMA_CTRL_TO_CLKDIV_DIV256                ((uint32_t)0x1UL) 
#define MXC_S_DMA_CTRL_TO_CLKDIV_DIV256                (MXC_V_DMA_CTRL_TO_CLKDIV_DIV256 << MXC_F_DMA_CTRL_TO_CLKDIV_POS) 
#define MXC_V_DMA_CTRL_TO_CLKDIV_DIV64K                ((uint32_t)0x2UL) 
#define MXC_S_DMA_CTRL_TO_CLKDIV_DIV64K                (MXC_V_DMA_CTRL_TO_CLKDIV_DIV64K << MXC_F_DMA_CTRL_TO_CLKDIV_POS) 
#define MXC_V_DMA_CTRL_TO_CLKDIV_DIV16M                ((uint32_t)0x3UL) 
#define MXC_S_DMA_CTRL_TO_CLKDIV_DIV16M                (MXC_V_DMA_CTRL_TO_CLKDIV_DIV16M << MXC_F_DMA_CTRL_TO_CLKDIV_POS) 
#define MXC_F_DMA_CTRL_SRCWD_POS                       16 
#define MXC_F_DMA_CTRL_SRCWD                           ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_SRCWD_POS)) 
#define MXC_V_DMA_CTRL_SRCWD_BYTE                      ((uint32_t)0x0UL) 
#define MXC_S_DMA_CTRL_SRCWD_BYTE                      (MXC_V_DMA_CTRL_SRCWD_BYTE << MXC_F_DMA_CTRL_SRCWD_POS) 
#define MXC_V_DMA_CTRL_SRCWD_HALFWORD                  ((uint32_t)0x1UL) 
#define MXC_S_DMA_CTRL_SRCWD_HALFWORD                  (MXC_V_DMA_CTRL_SRCWD_HALFWORD << MXC_F_DMA_CTRL_SRCWD_POS) 
#define MXC_V_DMA_CTRL_SRCWD_WORD                      ((uint32_t)0x2UL) 
#define MXC_S_DMA_CTRL_SRCWD_WORD                      (MXC_V_DMA_CTRL_SRCWD_WORD << MXC_F_DMA_CTRL_SRCWD_POS) 
#define MXC_F_DMA_CTRL_SRCINC_POS                      18 
#define MXC_F_DMA_CTRL_SRCINC                          ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_SRCINC_POS)) 
#define MXC_F_DMA_CTRL_DSTWD_POS                       20 
#define MXC_F_DMA_CTRL_DSTWD                           ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_DSTWD_POS)) 
#define MXC_V_DMA_CTRL_DSTWD_BYTE                      ((uint32_t)0x0UL) 
#define MXC_S_DMA_CTRL_DSTWD_BYTE                      (MXC_V_DMA_CTRL_DSTWD_BYTE << MXC_F_DMA_CTRL_DSTWD_POS) 
#define MXC_V_DMA_CTRL_DSTWD_HALFWORD                  ((uint32_t)0x1UL) 
#define MXC_S_DMA_CTRL_DSTWD_HALFWORD                  (MXC_V_DMA_CTRL_DSTWD_HALFWORD << MXC_F_DMA_CTRL_DSTWD_POS) 
#define MXC_V_DMA_CTRL_DSTWD_WORD                      ((uint32_t)0x2UL) 
#define MXC_S_DMA_CTRL_DSTWD_WORD                      (MXC_V_DMA_CTRL_DSTWD_WORD << MXC_F_DMA_CTRL_DSTWD_POS) 
#define MXC_F_DMA_CTRL_DSTINC_POS                      22 
#define MXC_F_DMA_CTRL_DSTINC                          ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_DSTINC_POS)) 
#define MXC_F_DMA_CTRL_BURST_SIZE_POS                  24 
#define MXC_F_DMA_CTRL_BURST_SIZE                      ((uint32_t)(0x1FUL << MXC_F_DMA_CTRL_BURST_SIZE_POS)) 
#define MXC_F_DMA_CTRL_DIS_IE_POS                      30 
#define MXC_F_DMA_CTRL_DIS_IE                          ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_DIS_IE_POS)) 
#define MXC_F_DMA_CTRL_CTZ_IE_POS                      31 
#define MXC_F_DMA_CTRL_CTZ_IE                          ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_CTZ_IE_POS)) 
#define MXC_F_DMA_STATUS_STATUS_POS                    0 
#define MXC_F_DMA_STATUS_STATUS                        ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_STATUS_POS)) 
#define MXC_F_DMA_STATUS_IPEND_POS                     1 
#define MXC_F_DMA_STATUS_IPEND                         ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_IPEND_POS)) 
#define MXC_F_DMA_STATUS_CTZ_IF_POS                    2 
#define MXC_F_DMA_STATUS_CTZ_IF                        ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_CTZ_IF_POS)) 
#define MXC_F_DMA_STATUS_RLD_IF_POS                    3 
#define MXC_F_DMA_STATUS_RLD_IF                        ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_RLD_IF_POS)) 
#define MXC_F_DMA_STATUS_BUS_ERR_POS                   4 
#define MXC_F_DMA_STATUS_BUS_ERR                       ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_BUS_ERR_POS)) 
#define MXC_F_DMA_STATUS_TO_IF_POS                     6 
#define MXC_F_DMA_STATUS_TO_IF                         ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_TO_IF_POS)) 
#define MXC_F_DMA_SRC_ADDR_POS                         0 
#define MXC_F_DMA_SRC_ADDR                             ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_SRC_ADDR_POS)) 
#define MXC_F_DMA_DST_ADDR_POS                         0 
#define MXC_F_DMA_DST_ADDR                             ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_DST_ADDR_POS)) 
#define MXC_F_DMA_CNT_CNT_POS                          0 
#define MXC_F_DMA_CNT_CNT                              ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_CNT_POS)) 
#define MXC_F_DMA_SRCRLD_ADDR_POS                      0 
#define MXC_F_DMA_SRCRLD_ADDR                          ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_SRCRLD_ADDR_POS)) 
#define MXC_F_DMA_DSTRLD_ADDR_POS                      0 
#define MXC_F_DMA_DSTRLD_ADDR                          ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_DSTRLD_ADDR_POS)) 
#define MXC_F_DMA_CNTRLD_CNT_POS                       0 
#define MXC_F_DMA_CNTRLD_CNT                           ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNTRLD_CNT_POS)) 
#define MXC_F_DMA_CNTRLD_EN_POS                        31 
#define MXC_F_DMA_CNTRLD_EN                            ((uint32_t)(0x1UL << MXC_F_DMA_CNTRLD_EN_POS)) 
#ifdef __cplusplus
}
#endif
 
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_DMA_REGS_H_