AES_INTEN

Macros
#define	MXC_F_AES_INTEN_DONE_POS   0
#define	MXC_F_AES_INTEN_DONE   ((uint32_t)(0x1UL << MXC_F_AES_INTEN_DONE_POS))
#define	MXC_F_AES_INTEN_KEY_CHANGE_POS   1
#define	MXC_F_AES_INTEN_KEY_CHANGE   ((uint32_t)(0x1UL << MXC_F_AES_INTEN_KEY_CHANGE_POS))
#define	MXC_F_AES_INTEN_KEY_ZERO_POS   2
#define	MXC_F_AES_INTEN_KEY_ZERO   ((uint32_t)(0x1UL << MXC_F_AES_INTEN_KEY_ZERO_POS))
#define	MXC_F_AES_INTEN_OV_POS   3
#define	MXC_F_AES_INTEN_OV   ((uint32_t)(0x1UL << MXC_F_AES_INTEN_OV_POS))
#define	MXC_F_AES_INTEN_KEY_ONE_POS   4
#define	MXC_F_AES_INTEN_KEY_ONE   ((uint32_t)(0x1UL << MXC_F_AES_INTEN_KEY_ONE_POS))

Detailed Description

AES Interrupt Enable Register.

Macro Definition Documentation

MXC_F_AES_INTEN_DONE

#define MXC_F_AES_INTEN_DONE   ((uint32_t)(0x1UL << MXC_F_AES_INTEN_DONE_POS))

INTEN_DONE Mask

MXC_F_AES_INTEN_DONE_POS

#define MXC_F_AES_INTEN_DONE_POS   0

INTEN_DONE Position

MXC_F_AES_INTEN_KEY_CHANGE

#define MXC_F_AES_INTEN_KEY_CHANGE   ((uint32_t)(0x1UL << MXC_F_AES_INTEN_KEY_CHANGE_POS))

INTEN_KEY_CHANGE Mask

MXC_F_AES_INTEN_KEY_CHANGE_POS

#define MXC_F_AES_INTEN_KEY_CHANGE_POS   1

INTEN_KEY_CHANGE Position

MXC_F_AES_INTEN_KEY_ONE

#define MXC_F_AES_INTEN_KEY_ONE   ((uint32_t)(0x1UL << MXC_F_AES_INTEN_KEY_ONE_POS))

INTEN_KEY_ONE Mask

MXC_F_AES_INTEN_KEY_ONE_POS

#define MXC_F_AES_INTEN_KEY_ONE_POS   4

INTEN_KEY_ONE Position

MXC_F_AES_INTEN_KEY_ZERO

#define MXC_F_AES_INTEN_KEY_ZERO   ((uint32_t)(0x1UL << MXC_F_AES_INTEN_KEY_ZERO_POS))

INTEN_KEY_ZERO Mask

MXC_F_AES_INTEN_KEY_ZERO_POS

#define MXC_F_AES_INTEN_KEY_ZERO_POS   2

INTEN_KEY_ZERO Position

MXC_F_AES_INTEN_OV

#define MXC_F_AES_INTEN_OV   ((uint32_t)(0x1UL << MXC_F_AES_INTEN_OV_POS))

INTEN_OV Mask

MXC_F_AES_INTEN_OV_POS

#define MXC_F_AES_INTEN_OV_POS   3

INTEN_OV Position