Register Offsets

Macros
#define	MXC_R_AES_CTRL   ((uint32_t)0x00000000UL)
#define	MXC_R_AES_STATUS   ((uint32_t)0x00000004UL)
#define	MXC_R_AES_INTFL   ((uint32_t)0x00000008UL)
#define	MXC_R_AES_INTEN   ((uint32_t)0x0000000CUL)
#define	MXC_R_AES_FIFO   ((uint32_t)0x00000010UL)

Detailed Description

AES Peripheral Register Offsets from the AES Base Peripheral Address.

Macro Definition Documentation

MXC_R_AES_CTRL

#define MXC_R_AES_CTRL   ((uint32_t)0x00000000UL)

Offset from AES Base Address: 0x0000

MXC_R_AES_FIFO

#define MXC_R_AES_FIFO   ((uint32_t)0x00000010UL)

Offset from AES Base Address: 0x0010

MXC_R_AES_INTEN

#define MXC_R_AES_INTEN   ((uint32_t)0x0000000CUL)

Offset from AES Base Address: 0x000C

MXC_R_AES_INTFL

#define MXC_R_AES_INTFL   ((uint32_t)0x00000008UL)

Offset from AES Base Address: 0x0008

MXC_R_AES_STATUS

#define MXC_R_AES_STATUS   ((uint32_t)0x00000004UL)

Offset from AES Base Address: 0x0004