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MAX32655 Peripheral Driver API
Peripheral Driver API for the MAX32655
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Macros | |
#define | MXC_F_GCR_MEMZ_RAM0_POS 0 |
#define | MXC_F_GCR_MEMZ_RAM0 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM0_POS)) |
#define | MXC_F_GCR_MEMZ_RAM1_POS 1 |
#define | MXC_F_GCR_MEMZ_RAM1 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM1_POS)) |
#define | MXC_F_GCR_MEMZ_RAM2_POS 2 |
#define | MXC_F_GCR_MEMZ_RAM2 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM2_POS)) |
#define | MXC_F_GCR_MEMZ_RAM3_POS 3 |
#define | MXC_F_GCR_MEMZ_RAM3 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM3_POS)) |
#define | MXC_F_GCR_MEMZ_SYSRAM0ECC_POS 4 |
#define | MXC_F_GCR_MEMZ_SYSRAM0ECC ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_SYSRAM0ECC_POS)) |
#define | MXC_F_GCR_MEMZ_ICC0_POS 5 |
#define | MXC_F_GCR_MEMZ_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_ICC0_POS)) |
#define | MXC_F_GCR_MEMZ_ICC1_POS 6 |
#define | MXC_F_GCR_MEMZ_ICC1 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_ICC1_POS)) |
Memory Zeroize Control.
#define MXC_F_GCR_MEMZ_ICC0 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_ICC0_POS)) |
MEMZ_ICC0 Mask
#define MXC_F_GCR_MEMZ_ICC0_POS 5 |
MEMZ_ICC0 Position
#define MXC_F_GCR_MEMZ_ICC1 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_ICC1_POS)) |
MEMZ_ICC1 Mask
#define MXC_F_GCR_MEMZ_ICC1_POS 6 |
MEMZ_ICC1 Position
#define MXC_F_GCR_MEMZ_RAM0 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM0_POS)) |
MEMZ_RAM0 Mask
#define MXC_F_GCR_MEMZ_RAM0_POS 0 |
MEMZ_RAM0 Position
#define MXC_F_GCR_MEMZ_RAM1 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM1_POS)) |
MEMZ_RAM1 Mask
#define MXC_F_GCR_MEMZ_RAM1_POS 1 |
MEMZ_RAM1 Position
#define MXC_F_GCR_MEMZ_RAM2 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM2_POS)) |
MEMZ_RAM2 Mask
#define MXC_F_GCR_MEMZ_RAM2_POS 2 |
MEMZ_RAM2 Position
#define MXC_F_GCR_MEMZ_RAM3 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM3_POS)) |
MEMZ_RAM3 Mask
#define MXC_F_GCR_MEMZ_RAM3_POS 3 |
MEMZ_RAM3 Position
#define MXC_F_GCR_MEMZ_SYSRAM0ECC ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_SYSRAM0ECC_POS)) |
MEMZ_SYSRAM0ECC Mask
#define MXC_F_GCR_MEMZ_SYSRAM0ECC_POS 4 |
MEMZ_SYSRAM0ECC Position