Macros
#define	MXC_F_GCR_RST1_I2C1_POS 0

#define	MXC_F_GCR_RST1_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C1_POS))

#define	MXC_F_GCR_RST1_PT_POS 1

#define	MXC_F_GCR_RST1_PT ((uint32_t)(0x1UL << MXC_F_GCR_RST1_PT_POS))

#define	MXC_F_GCR_RST1_OWM_POS 7

#define	MXC_F_GCR_RST1_OWM ((uint32_t)(0x1UL << MXC_F_GCR_RST1_OWM_POS))

#define	MXC_F_GCR_RST1_CRC_POS 9

#define	MXC_F_GCR_RST1_CRC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_CRC_POS))

#define	MXC_F_GCR_RST1_AES_POS 10

#define	MXC_F_GCR_RST1_AES ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AES_POS))

#define	MXC_F_GCR_RST1_SPI0_POS 11

#define	MXC_F_GCR_RST1_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SPI0_POS))

#define	MXC_F_GCR_RST1_SMPHR_POS 16

#define	MXC_F_GCR_RST1_SMPHR ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SMPHR_POS))

#define	MXC_F_GCR_RST1_I2S_POS 19

#define	MXC_F_GCR_RST1_I2S ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2S_POS))

#define	MXC_F_GCR_RST1_I2C2_POS 20

#define	MXC_F_GCR_RST1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C2_POS))

#define	MXC_F_GCR_RST1_DVS_POS 24

#define	MXC_F_GCR_RST1_DVS ((uint32_t)(0x1UL << MXC_F_GCR_RST1_DVS_POS))

#define	MXC_F_GCR_RST1_SIMO_POS 25

#define	MXC_F_GCR_RST1_SIMO ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SIMO_POS))

#define	MXC_F_GCR_RST1_CPU1_POS 31

#define	MXC_F_GCR_RST1_CPU1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_CPU1_POS))

Detailed Description

Reset 1.

Macro Definition Documentation

◆ MXC_F_GCR_RST1_AES

#define MXC_F_GCR_RST1_AES ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AES_POS))

RST1_AES Mask

◆ MXC_F_GCR_RST1_AES_POS

#define MXC_F_GCR_RST1_AES_POS 10

RST1_AES Position

◆ MXC_F_GCR_RST1_CPU1

#define MXC_F_GCR_RST1_CPU1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_CPU1_POS))

RST1_CPU1 Mask

◆ MXC_F_GCR_RST1_CPU1_POS

#define MXC_F_GCR_RST1_CPU1_POS 31

RST1_CPU1 Position

◆ MXC_F_GCR_RST1_CRC

#define MXC_F_GCR_RST1_CRC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_CRC_POS))

RST1_CRC Mask

◆ MXC_F_GCR_RST1_CRC_POS

#define MXC_F_GCR_RST1_CRC_POS 9

RST1_CRC Position

◆ MXC_F_GCR_RST1_DVS

#define MXC_F_GCR_RST1_DVS ((uint32_t)(0x1UL << MXC_F_GCR_RST1_DVS_POS))

RST1_DVS Mask

◆ MXC_F_GCR_RST1_DVS_POS

#define MXC_F_GCR_RST1_DVS_POS 24

RST1_DVS Position

◆ MXC_F_GCR_RST1_I2C1

#define MXC_F_GCR_RST1_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C1_POS))

RST1_I2C1 Mask

◆ MXC_F_GCR_RST1_I2C1_POS

#define MXC_F_GCR_RST1_I2C1_POS 0

RST1_I2C1 Position

◆ MXC_F_GCR_RST1_I2C2

#define MXC_F_GCR_RST1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C2_POS))

RST1_I2C2 Mask

◆ MXC_F_GCR_RST1_I2C2_POS

#define MXC_F_GCR_RST1_I2C2_POS 20

RST1_I2C2 Position

◆ MXC_F_GCR_RST1_I2S

#define MXC_F_GCR_RST1_I2S ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2S_POS))

RST1_I2S Mask

◆ MXC_F_GCR_RST1_I2S_POS

#define MXC_F_GCR_RST1_I2S_POS 19

RST1_I2S Position

◆ MXC_F_GCR_RST1_OWM

#define MXC_F_GCR_RST1_OWM ((uint32_t)(0x1UL << MXC_F_GCR_RST1_OWM_POS))

RST1_OWM Mask

◆ MXC_F_GCR_RST1_OWM_POS

#define MXC_F_GCR_RST1_OWM_POS 7

RST1_OWM Position

◆ MXC_F_GCR_RST1_PT

#define MXC_F_GCR_RST1_PT ((uint32_t)(0x1UL << MXC_F_GCR_RST1_PT_POS))

RST1_PT Mask

◆ MXC_F_GCR_RST1_PT_POS

#define MXC_F_GCR_RST1_PT_POS 1

RST1_PT Position

◆ MXC_F_GCR_RST1_SIMO

#define MXC_F_GCR_RST1_SIMO ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SIMO_POS))

RST1_SIMO Mask

◆ MXC_F_GCR_RST1_SIMO_POS

#define MXC_F_GCR_RST1_SIMO_POS 25

RST1_SIMO Position

◆ MXC_F_GCR_RST1_SMPHR

#define MXC_F_GCR_RST1_SMPHR ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SMPHR_POS))

RST1_SMPHR Mask

◆ MXC_F_GCR_RST1_SMPHR_POS

#define MXC_F_GCR_RST1_SMPHR_POS 16

RST1_SMPHR Position

◆ MXC_F_GCR_RST1_SPI0

#define MXC_F_GCR_RST1_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SPI0_POS))

RST1_SPI0 Mask

◆ MXC_F_GCR_RST1_SPI0_POS

#define MXC_F_GCR_RST1_SPI0_POS 11

RST1_SPI0 Position

Macros