I2S_INTFL

Macros
#define	MXC_F_I2S_INTFL_RX_OV_CH0_POS   0
#define	MXC_F_I2S_INTFL_RX_OV_CH0   ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_RX_OV_CH0_POS))
#define	MXC_F_I2S_INTFL_RX_THD_CH0_POS   1
#define	MXC_F_I2S_INTFL_RX_THD_CH0   ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_RX_THD_CH0_POS))
#define	MXC_F_I2S_INTFL_TX_OB_CH0_POS   2
#define	MXC_F_I2S_INTFL_TX_OB_CH0   ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_TX_OB_CH0_POS))
#define	MXC_F_I2S_INTFL_TX_HE_CH0_POS   3
#define	MXC_F_I2S_INTFL_TX_HE_CH0   ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_TX_HE_CH0_POS))

Detailed Description

ISR Status.

Macro Definition Documentation

MXC_F_I2S_INTFL_RX_OV_CH0

#define MXC_F_I2S_INTFL_RX_OV_CH0   ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_RX_OV_CH0_POS))

INTFL_RX_OV_CH0 Mask

MXC_F_I2S_INTFL_RX_OV_CH0_POS

#define MXC_F_I2S_INTFL_RX_OV_CH0_POS   0

INTFL_RX_OV_CH0 Position

MXC_F_I2S_INTFL_RX_THD_CH0

#define MXC_F_I2S_INTFL_RX_THD_CH0   ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_RX_THD_CH0_POS))

INTFL_RX_THD_CH0 Mask

MXC_F_I2S_INTFL_RX_THD_CH0_POS

#define MXC_F_I2S_INTFL_RX_THD_CH0_POS   1

INTFL_RX_THD_CH0 Position

MXC_F_I2S_INTFL_TX_HE_CH0

#define MXC_F_I2S_INTFL_TX_HE_CH0   ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_TX_HE_CH0_POS))

INTFL_TX_HE_CH0 Mask

MXC_F_I2S_INTFL_TX_HE_CH0_POS

#define MXC_F_I2S_INTFL_TX_HE_CH0_POS   3

INTFL_TX_HE_CH0 Position

MXC_F_I2S_INTFL_TX_OB_CH0

#define MXC_F_I2S_INTFL_TX_OB_CH0   ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_TX_OB_CH0_POS))

INTFL_TX_OB_CH0 Mask

MXC_F_I2S_INTFL_TX_OB_CH0_POS

#define MXC_F_I2S_INTFL_TX_OB_CH0_POS   2

INTFL_TX_OB_CH0 Position