Macros
#define	MXC_F_LPGCR_RST_GPIO2_POS 0

#define	MXC_F_LPGCR_RST_GPIO2 ((uint32_t)(0x1UL << MXC_F_LPGCR_RST_GPIO2_POS))

#define	MXC_F_LPGCR_RST_WDT1_POS 1

#define	MXC_F_LPGCR_RST_WDT1 ((uint32_t)(0x1UL << MXC_F_LPGCR_RST_WDT1_POS))

#define	MXC_F_LPGCR_RST_TMR4_POS 2

#define	MXC_F_LPGCR_RST_TMR4 ((uint32_t)(0x1UL << MXC_F_LPGCR_RST_TMR4_POS))

#define	MXC_F_LPGCR_RST_TMR5_POS 3

#define	MXC_F_LPGCR_RST_TMR5 ((uint32_t)(0x1UL << MXC_F_LPGCR_RST_TMR5_POS))

#define	MXC_F_LPGCR_RST_UART3_POS 4

#define	MXC_F_LPGCR_RST_UART3 ((uint32_t)(0x1UL << MXC_F_LPGCR_RST_UART3_POS))

#define	MXC_F_LPGCR_RST_LPCOMP_POS 6

#define	MXC_F_LPGCR_RST_LPCOMP ((uint32_t)(0x1UL << MXC_F_LPGCR_RST_LPCOMP_POS))

Detailed Description

Low Power Reset Register.

Macro Definition Documentation

◆ MXC_F_LPGCR_RST_GPIO2

#define MXC_F_LPGCR_RST_GPIO2 ((uint32_t)(0x1UL << MXC_F_LPGCR_RST_GPIO2_POS))

RST_GPIO2 Mask

◆ MXC_F_LPGCR_RST_GPIO2_POS

#define MXC_F_LPGCR_RST_GPIO2_POS 0

RST_GPIO2 Position

◆ MXC_F_LPGCR_RST_LPCOMP

#define MXC_F_LPGCR_RST_LPCOMP ((uint32_t)(0x1UL << MXC_F_LPGCR_RST_LPCOMP_POS))

RST_LPCOMP Mask

◆ MXC_F_LPGCR_RST_LPCOMP_POS

#define MXC_F_LPGCR_RST_LPCOMP_POS 6

RST_LPCOMP Position

◆ MXC_F_LPGCR_RST_TMR4

#define MXC_F_LPGCR_RST_TMR4 ((uint32_t)(0x1UL << MXC_F_LPGCR_RST_TMR4_POS))

RST_TMR4 Mask

◆ MXC_F_LPGCR_RST_TMR4_POS

#define MXC_F_LPGCR_RST_TMR4_POS 2

RST_TMR4 Position

◆ MXC_F_LPGCR_RST_TMR5

#define MXC_F_LPGCR_RST_TMR5 ((uint32_t)(0x1UL << MXC_F_LPGCR_RST_TMR5_POS))

RST_TMR5 Mask

◆ MXC_F_LPGCR_RST_TMR5_POS

#define MXC_F_LPGCR_RST_TMR5_POS 3

RST_TMR5 Position

◆ MXC_F_LPGCR_RST_UART3

#define MXC_F_LPGCR_RST_UART3 ((uint32_t)(0x1UL << MXC_F_LPGCR_RST_UART3_POS))

RST_UART3 Mask

◆ MXC_F_LPGCR_RST_UART3_POS

#define MXC_F_LPGCR_RST_UART3_POS 4

RST_UART3 Position

◆ MXC_F_LPGCR_RST_WDT1

#define MXC_F_LPGCR_RST_WDT1 ((uint32_t)(0x1UL << MXC_F_LPGCR_RST_WDT1_POS))

RST_WDT1 Mask

◆ MXC_F_LPGCR_RST_WDT1_POS

#define MXC_F_LPGCR_RST_WDT1_POS 1

RST_WDT1 Position

Macros