Macros
#define	MXC_F_OWM_INTEN_OW_RESET_DONE_POS 0

#define	MXC_F_OWM_INTEN_OW_RESET_DONE ((uint32_t)(0x1UL << MXC_F_OWM_INTEN_OW_RESET_DONE_POS))

#define	MXC_F_OWM_INTEN_TX_DATA_EMPTY_POS 1

#define	MXC_F_OWM_INTEN_TX_DATA_EMPTY ((uint32_t)(0x1UL << MXC_F_OWM_INTEN_TX_DATA_EMPTY_POS))

#define	MXC_F_OWM_INTEN_RX_DATA_READY_POS 2

#define	MXC_F_OWM_INTEN_RX_DATA_READY ((uint32_t)(0x1UL << MXC_F_OWM_INTEN_RX_DATA_READY_POS))

#define	MXC_F_OWM_INTEN_LINE_SHORT_POS 3

#define	MXC_F_OWM_INTEN_LINE_SHORT ((uint32_t)(0x1UL << MXC_F_OWM_INTEN_LINE_SHORT_POS))

#define	MXC_F_OWM_INTEN_LINE_LOW_POS 4

#define	MXC_F_OWM_INTEN_LINE_LOW ((uint32_t)(0x1UL << MXC_F_OWM_INTEN_LINE_LOW_POS))

Detailed Description

1-Wire Master Interrupt Enables.

Macro Definition Documentation

#define MXC_F_OWM_INTEN_LINE_LOW ((uint32_t)(0x1UL << MXC_F_OWM_INTEN_LINE_LOW_POS))

INTEN_LINE_LOW Mask

#define MXC_F_OWM_INTEN_LINE_LOW_POS 4

INTEN_LINE_LOW Position

#define MXC_F_OWM_INTEN_LINE_SHORT ((uint32_t)(0x1UL << MXC_F_OWM_INTEN_LINE_SHORT_POS))

INTEN_LINE_SHORT Mask

#define MXC_F_OWM_INTEN_LINE_SHORT_POS 3

INTEN_LINE_SHORT Position

#define MXC_F_OWM_INTEN_OW_RESET_DONE ((uint32_t)(0x1UL << MXC_F_OWM_INTEN_OW_RESET_DONE_POS))

INTEN_OW_RESET_DONE Mask

#define MXC_F_OWM_INTEN_OW_RESET_DONE_POS 0

INTEN_OW_RESET_DONE Position

#define MXC_F_OWM_INTEN_RX_DATA_READY ((uint32_t)(0x1UL << MXC_F_OWM_INTEN_RX_DATA_READY_POS))

INTEN_RX_DATA_READY Mask

#define MXC_F_OWM_INTEN_RX_DATA_READY_POS 2

INTEN_RX_DATA_READY Position

#define MXC_F_OWM_INTEN_TX_DATA_EMPTY ((uint32_t)(0x1UL << MXC_F_OWM_INTEN_TX_DATA_EMPTY_POS))

INTEN_TX_DATA_EMPTY Mask

#define MXC_F_OWM_INTEN_TX_DATA_EMPTY_POS 1

INTEN_TX_DATA_EMPTY Position