Register Offsets

Macros
#define	MXC_R_SEMA_SEMAPHORES   ((uint32_t)0x00000000UL)
#define	MXC_R_SEMA_IRQ0   ((uint32_t)0x00000040UL)
#define	MXC_R_SEMA_MAIL0   ((uint32_t)0x00000044UL)
#define	MXC_R_SEMA_IRQ1   ((uint32_t)0x00000048UL)
#define	MXC_R_SEMA_MAIL1   ((uint32_t)0x0000004CUL)
#define	MXC_R_SEMA_STATUS   ((uint32_t)0x00000100UL)

Detailed Description

SEMA Peripheral Register Offsets from the SEMA Base Peripheral Address.

Macro Definition Documentation

MXC_R_SEMA_IRQ0

#define MXC_R_SEMA_IRQ0   ((uint32_t)0x00000040UL)

Offset from SEMA Base Address: 0x0040

MXC_R_SEMA_IRQ1

#define MXC_R_SEMA_IRQ1   ((uint32_t)0x00000048UL)

Offset from SEMA Base Address: 0x0048

MXC_R_SEMA_MAIL0

#define MXC_R_SEMA_MAIL0   ((uint32_t)0x00000044UL)

Offset from SEMA Base Address: 0x0044

MXC_R_SEMA_MAIL1

#define MXC_R_SEMA_MAIL1   ((uint32_t)0x0000004CUL)

Offset from SEMA Base Address: 0x004C

MXC_R_SEMA_SEMAPHORES

#define MXC_R_SEMA_SEMAPHORES   ((uint32_t)0x00000000UL)

Offset from SEMA Base Address: 0x0000

MXC_R_SEMA_STATUS

#define MXC_R_SEMA_STATUS   ((uint32_t)0x00000100UL)

Offset from SEMA Base Address: 0x0100