SPI_INTFL

Macros
#define	MXC_F_SPI_INTFL_TX_THD_POS   0
#define	MXC_F_SPI_INTFL_TX_THD   ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_THD_POS))
#define	MXC_F_SPI_INTFL_TX_EM_POS   1
#define	MXC_F_SPI_INTFL_TX_EM   ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_EM_POS))
#define	MXC_F_SPI_INTFL_RX_THD_POS   2
#define	MXC_F_SPI_INTFL_RX_THD   ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_THD_POS))
#define	MXC_F_SPI_INTFL_RX_FULL_POS   3
#define	MXC_F_SPI_INTFL_RX_FULL   ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_FULL_POS))
#define	MXC_F_SPI_INTFL_SSA_POS   4
#define	MXC_F_SPI_INTFL_SSA   ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_SSA_POS))
#define	MXC_F_SPI_INTFL_SSD_POS   5
#define	MXC_F_SPI_INTFL_SSD   ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_SSD_POS))
#define	MXC_F_SPI_INTFL_FAULT_POS   8
#define	MXC_F_SPI_INTFL_FAULT   ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_FAULT_POS))
#define	MXC_F_SPI_INTFL_ABORT_POS   9
#define	MXC_F_SPI_INTFL_ABORT   ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_ABORT_POS))
#define	MXC_F_SPI_INTFL_MST_DONE_POS   11
#define	MXC_F_SPI_INTFL_MST_DONE   ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_MST_DONE_POS))
#define	MXC_F_SPI_INTFL_TX_OV_POS   12
#define	MXC_F_SPI_INTFL_TX_OV   ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_OV_POS))
#define	MXC_F_SPI_INTFL_TX_UN_POS   13
#define	MXC_F_SPI_INTFL_TX_UN   ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_UN_POS))
#define	MXC_F_SPI_INTFL_RX_OV_POS   14
#define	MXC_F_SPI_INTFL_RX_OV   ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_OV_POS))
#define	MXC_F_SPI_INTFL_RX_UN_POS   15
#define	MXC_F_SPI_INTFL_RX_UN   ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_UN_POS))

Detailed Description

Register for reading and clearing interrupt flags. All bits are write 1 to clear.

Macro Definition Documentation

MXC_F_SPI_INTFL_ABORT

#define MXC_F_SPI_INTFL_ABORT   ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_ABORT_POS))

INTFL_ABORT Mask

MXC_F_SPI_INTFL_ABORT_POS

#define MXC_F_SPI_INTFL_ABORT_POS   9

INTFL_ABORT Position

MXC_F_SPI_INTFL_FAULT

#define MXC_F_SPI_INTFL_FAULT   ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_FAULT_POS))

INTFL_FAULT Mask

MXC_F_SPI_INTFL_FAULT_POS

#define MXC_F_SPI_INTFL_FAULT_POS   8

INTFL_FAULT Position

MXC_F_SPI_INTFL_MST_DONE

#define MXC_F_SPI_INTFL_MST_DONE   ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_MST_DONE_POS))

INTFL_MST_DONE Mask

MXC_F_SPI_INTFL_MST_DONE_POS

#define MXC_F_SPI_INTFL_MST_DONE_POS   11

INTFL_MST_DONE Position

MXC_F_SPI_INTFL_RX_FULL

#define MXC_F_SPI_INTFL_RX_FULL   ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_FULL_POS))

INTFL_RX_FULL Mask

MXC_F_SPI_INTFL_RX_FULL_POS

#define MXC_F_SPI_INTFL_RX_FULL_POS   3

INTFL_RX_FULL Position

MXC_F_SPI_INTFL_RX_OV

#define MXC_F_SPI_INTFL_RX_OV   ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_OV_POS))

INTFL_RX_OV Mask

MXC_F_SPI_INTFL_RX_OV_POS

#define MXC_F_SPI_INTFL_RX_OV_POS   14

INTFL_RX_OV Position

MXC_F_SPI_INTFL_RX_THD

#define MXC_F_SPI_INTFL_RX_THD   ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_THD_POS))

INTFL_RX_THD Mask

MXC_F_SPI_INTFL_RX_THD_POS

#define MXC_F_SPI_INTFL_RX_THD_POS   2

INTFL_RX_THD Position

MXC_F_SPI_INTFL_RX_UN

#define MXC_F_SPI_INTFL_RX_UN   ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_UN_POS))

INTFL_RX_UN Mask

MXC_F_SPI_INTFL_RX_UN_POS

#define MXC_F_SPI_INTFL_RX_UN_POS   15

INTFL_RX_UN Position

MXC_F_SPI_INTFL_SSA

#define MXC_F_SPI_INTFL_SSA   ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_SSA_POS))

INTFL_SSA Mask

MXC_F_SPI_INTFL_SSA_POS

#define MXC_F_SPI_INTFL_SSA_POS   4

INTFL_SSA Position

MXC_F_SPI_INTFL_SSD

#define MXC_F_SPI_INTFL_SSD   ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_SSD_POS))

INTFL_SSD Mask

MXC_F_SPI_INTFL_SSD_POS

#define MXC_F_SPI_INTFL_SSD_POS   5

INTFL_SSD Position

MXC_F_SPI_INTFL_TX_EM

#define MXC_F_SPI_INTFL_TX_EM   ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_EM_POS))

INTFL_TX_EM Mask

MXC_F_SPI_INTFL_TX_EM_POS

#define MXC_F_SPI_INTFL_TX_EM_POS   1

INTFL_TX_EM Position

MXC_F_SPI_INTFL_TX_OV

#define MXC_F_SPI_INTFL_TX_OV   ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_OV_POS))

INTFL_TX_OV Mask

MXC_F_SPI_INTFL_TX_OV_POS

#define MXC_F_SPI_INTFL_TX_OV_POS   12

INTFL_TX_OV Position

MXC_F_SPI_INTFL_TX_THD

#define MXC_F_SPI_INTFL_TX_THD   ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_THD_POS))

INTFL_TX_THD Mask

MXC_F_SPI_INTFL_TX_THD_POS

#define MXC_F_SPI_INTFL_TX_THD_POS   0

INTFL_TX_THD Position

MXC_F_SPI_INTFL_TX_UN

#define MXC_F_SPI_INTFL_TX_UN   ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_UN_POS))

INTFL_TX_UN Mask

MXC_F_SPI_INTFL_TX_UN_POS

#define MXC_F_SPI_INTFL_TX_UN_POS   13

INTFL_TX_UN Position