Macros
#define	MXC_F_DMA_STAT_CH_ST_POS 0

#define	MXC_F_DMA_STAT_CH_ST ((uint32_t)(0x1UL << MXC_F_DMA_STAT_CH_ST_POS))

#define	MXC_F_DMA_STAT_IPEND_POS 1

#define	MXC_F_DMA_STAT_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_STAT_IPEND_POS))

#define	MXC_F_DMA_STAT_CTZ_ST_POS 2

#define	MXC_F_DMA_STAT_CTZ_ST ((uint32_t)(0x1UL << MXC_F_DMA_STAT_CTZ_ST_POS))

#define	MXC_F_DMA_STAT_RLD_ST_POS 3

#define	MXC_F_DMA_STAT_RLD_ST ((uint32_t)(0x1UL << MXC_F_DMA_STAT_RLD_ST_POS))

#define	MXC_F_DMA_STAT_BUS_ERR_POS 4

#define	MXC_F_DMA_STAT_BUS_ERR ((uint32_t)(0x1UL << MXC_F_DMA_STAT_BUS_ERR_POS))

#define	MXC_F_DMA_STAT_TO_ST_POS 6

#define	MXC_F_DMA_STAT_TO_ST ((uint32_t)(0x1UL << MXC_F_DMA_STAT_TO_ST_POS))

Detailed Description

DMA Channel Status Register.

Macro Definition Documentation

◆ MXC_F_DMA_STAT_BUS_ERR

#define MXC_F_DMA_STAT_BUS_ERR ((uint32_t)(0x1UL << MXC_F_DMA_STAT_BUS_ERR_POS))

STAT_BUS_ERR Mask

◆ MXC_F_DMA_STAT_BUS_ERR_POS

#define MXC_F_DMA_STAT_BUS_ERR_POS 4

STAT_BUS_ERR Position

◆ MXC_F_DMA_STAT_CH_ST

#define MXC_F_DMA_STAT_CH_ST ((uint32_t)(0x1UL << MXC_F_DMA_STAT_CH_ST_POS))

STAT_CH_ST Mask

◆ MXC_F_DMA_STAT_CH_ST_POS

#define MXC_F_DMA_STAT_CH_ST_POS 0

STAT_CH_ST Position

◆ MXC_F_DMA_STAT_CTZ_ST

#define MXC_F_DMA_STAT_CTZ_ST ((uint32_t)(0x1UL << MXC_F_DMA_STAT_CTZ_ST_POS))

STAT_CTZ_ST Mask

◆ MXC_F_DMA_STAT_CTZ_ST_POS

#define MXC_F_DMA_STAT_CTZ_ST_POS 2

STAT_CTZ_ST Position

◆ MXC_F_DMA_STAT_IPEND

#define MXC_F_DMA_STAT_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_STAT_IPEND_POS))

STAT_IPEND Mask

◆ MXC_F_DMA_STAT_IPEND_POS

#define MXC_F_DMA_STAT_IPEND_POS 1

STAT_IPEND Position

◆ MXC_F_DMA_STAT_RLD_ST

#define MXC_F_DMA_STAT_RLD_ST ((uint32_t)(0x1UL << MXC_F_DMA_STAT_RLD_ST_POS))

STAT_RLD_ST Mask

◆ MXC_F_DMA_STAT_RLD_ST_POS

#define MXC_F_DMA_STAT_RLD_ST_POS 3

STAT_RLD_ST Position

◆ MXC_F_DMA_STAT_TO_ST

#define MXC_F_DMA_STAT_TO_ST ((uint32_t)(0x1UL << MXC_F_DMA_STAT_TO_ST_POS))

STAT_TO_ST Mask

◆ MXC_F_DMA_STAT_TO_ST_POS

#define MXC_F_DMA_STAT_TO_ST_POS 6

STAT_TO_ST Position

Macros