FCR_REG0

Macros
#define	MXC_F_FCR_REG0_I2C0_SDA_FILTER_EN_POS   20
#define	MXC_F_FCR_REG0_I2C0_SDA_FILTER_EN   ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C0_SDA_FILTER_EN_POS))
#define	MXC_F_FCR_REG0_I2C0_SCL_FILTER_EN_POS   21
#define	MXC_F_FCR_REG0_I2C0_SCL_FILTER_EN   ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C0_SCL_FILTER_EN_POS))
#define	MXC_F_FCR_REG0_I2C1_SDA_FILTER_EN_POS   22
#define	MXC_F_FCR_REG0_I2C1_SDA_FILTER_EN   ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C1_SDA_FILTER_EN_POS))
#define	MXC_F_FCR_REG0_I2C1_SCL_FILTER_EN_POS   23
#define	MXC_F_FCR_REG0_I2C1_SCL_FILTER_EN   ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C1_SCL_FILTER_EN_POS))

Detailed Description

Register 0.

Macro Definition Documentation

MXC_F_FCR_REG0_I2C0_SCL_FILTER_EN

#define MXC_F_FCR_REG0_I2C0_SCL_FILTER_EN   ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C0_SCL_FILTER_EN_POS))

REG0_I2C0_SCL_FILTER_EN Mask

MXC_F_FCR_REG0_I2C0_SCL_FILTER_EN_POS

#define MXC_F_FCR_REG0_I2C0_SCL_FILTER_EN_POS   21

REG0_I2C0_SCL_FILTER_EN Position

MXC_F_FCR_REG0_I2C0_SDA_FILTER_EN

#define MXC_F_FCR_REG0_I2C0_SDA_FILTER_EN   ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C0_SDA_FILTER_EN_POS))

REG0_I2C0_SDA_FILTER_EN Mask

MXC_F_FCR_REG0_I2C0_SDA_FILTER_EN_POS

#define MXC_F_FCR_REG0_I2C0_SDA_FILTER_EN_POS   20

REG0_I2C0_SDA_FILTER_EN Position

MXC_F_FCR_REG0_I2C1_SCL_FILTER_EN

#define MXC_F_FCR_REG0_I2C1_SCL_FILTER_EN   ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C1_SCL_FILTER_EN_POS))

REG0_I2C1_SCL_FILTER_EN Mask

MXC_F_FCR_REG0_I2C1_SCL_FILTER_EN_POS

#define MXC_F_FCR_REG0_I2C1_SCL_FILTER_EN_POS   23

REG0_I2C1_SCL_FILTER_EN Position

MXC_F_FCR_REG0_I2C1_SDA_FILTER_EN

#define MXC_F_FCR_REG0_I2C1_SDA_FILTER_EN   ((uint32_t)(0x1UL << MXC_F_FCR_REG0_I2C1_SDA_FILTER_EN_POS))

REG0_I2C1_SDA_FILTER_EN Mask

MXC_F_FCR_REG0_I2C1_SDA_FILTER_EN_POS

#define MXC_F_FCR_REG0_I2C1_SDA_FILTER_EN_POS   22

REG0_I2C1_SDA_FILTER_EN Position