GCR_RST0

Macros
#define	MXC_F_GCR_RST0_DMA_POS   0
#define	MXC_F_GCR_RST0_DMA   ((uint32_t)(0x1UL << MXC_F_GCR_RST0_DMA_POS))
#define	MXC_F_GCR_RST0_WDT0_POS   1
#define	MXC_F_GCR_RST0_WDT0   ((uint32_t)(0x1UL << MXC_F_GCR_RST0_WDT0_POS))
#define	MXC_F_GCR_RST0_GPIO0_POS   2
#define	MXC_F_GCR_RST0_GPIO0   ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO0_POS))
#define	MXC_F_GCR_RST0_TIMER0_POS   5
#define	MXC_F_GCR_RST0_TIMER0   ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER0_POS))
#define	MXC_F_GCR_RST0_TIMER1_POS   6
#define	MXC_F_GCR_RST0_TIMER1   ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER1_POS))
#define	MXC_F_GCR_RST0_TIMER2_POS   7
#define	MXC_F_GCR_RST0_TIMER2   ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER2_POS))
#define	MXC_F_GCR_RST0_UART0_POS   11
#define	MXC_F_GCR_RST0_UART0   ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART0_POS))
#define	MXC_F_GCR_RST0_UART1_POS   12
#define	MXC_F_GCR_RST0_UART1   ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART1_POS))
#define	MXC_F_GCR_RST0_SPI0_POS   13
#define	MXC_F_GCR_RST0_SPI0   ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI0_POS))
#define	MXC_F_GCR_RST0_SPI1_POS   14
#define	MXC_F_GCR_RST0_SPI1   ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI1_POS))
#define	MXC_F_GCR_RST0_I2C0_POS   16
#define	MXC_F_GCR_RST0_I2C0   ((uint32_t)(0x1UL << MXC_F_GCR_RST0_I2C0_POS))
#define	MXC_F_GCR_RST0_RTC_POS   17
#define	MXC_F_GCR_RST0_RTC   ((uint32_t)(0x1UL << MXC_F_GCR_RST0_RTC_POS))
#define	MXC_F_GCR_RST0_SOFT_POS   29
#define	MXC_F_GCR_RST0_SOFT   ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SOFT_POS))
#define	MXC_F_GCR_RST0_PERIPH_POS   30
#define	MXC_F_GCR_RST0_PERIPH   ((uint32_t)(0x1UL << MXC_F_GCR_RST0_PERIPH_POS))
#define	MXC_F_GCR_RST0_SYSTEM_POS   31
#define	MXC_F_GCR_RST0_SYSTEM   ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SYSTEM_POS))

Detailed Description

Reset.

Macro Definition Documentation

MXC_F_GCR_RST0_DMA

#define MXC_F_GCR_RST0_DMA   ((uint32_t)(0x1UL << MXC_F_GCR_RST0_DMA_POS))

RST0_DMA Mask

MXC_F_GCR_RST0_DMA_POS

#define MXC_F_GCR_RST0_DMA_POS   0

RST0_DMA Position

MXC_F_GCR_RST0_GPIO0

#define MXC_F_GCR_RST0_GPIO0   ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO0_POS))

RST0_GPIO0 Mask

MXC_F_GCR_RST0_GPIO0_POS

#define MXC_F_GCR_RST0_GPIO0_POS   2

RST0_GPIO0 Position

MXC_F_GCR_RST0_I2C0

#define MXC_F_GCR_RST0_I2C0   ((uint32_t)(0x1UL << MXC_F_GCR_RST0_I2C0_POS))

RST0_I2C0 Mask

MXC_F_GCR_RST0_I2C0_POS

#define MXC_F_GCR_RST0_I2C0_POS   16

RST0_I2C0 Position

MXC_F_GCR_RST0_PERIPH

#define MXC_F_GCR_RST0_PERIPH   ((uint32_t)(0x1UL << MXC_F_GCR_RST0_PERIPH_POS))

RST0_PERIPH Mask

MXC_F_GCR_RST0_PERIPH_POS

#define MXC_F_GCR_RST0_PERIPH_POS   30

RST0_PERIPH Position

MXC_F_GCR_RST0_RTC

#define MXC_F_GCR_RST0_RTC   ((uint32_t)(0x1UL << MXC_F_GCR_RST0_RTC_POS))

RST0_RTC Mask

MXC_F_GCR_RST0_RTC_POS

#define MXC_F_GCR_RST0_RTC_POS   17

RST0_RTC Position

MXC_F_GCR_RST0_SOFT

#define MXC_F_GCR_RST0_SOFT   ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SOFT_POS))

RST0_SOFT Mask

MXC_F_GCR_RST0_SOFT_POS

#define MXC_F_GCR_RST0_SOFT_POS   29

RST0_SOFT Position

MXC_F_GCR_RST0_SPI0

#define MXC_F_GCR_RST0_SPI0   ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI0_POS))

RST0_SPI0 Mask

MXC_F_GCR_RST0_SPI0_POS

#define MXC_F_GCR_RST0_SPI0_POS   13

RST0_SPI0 Position

MXC_F_GCR_RST0_SPI1

#define MXC_F_GCR_RST0_SPI1   ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI1_POS))

RST0_SPI1 Mask

MXC_F_GCR_RST0_SPI1_POS

#define MXC_F_GCR_RST0_SPI1_POS   14

RST0_SPI1 Position

MXC_F_GCR_RST0_SYSTEM

#define MXC_F_GCR_RST0_SYSTEM   ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SYSTEM_POS))

RST0_SYSTEM Mask

MXC_F_GCR_RST0_SYSTEM_POS

#define MXC_F_GCR_RST0_SYSTEM_POS   31

RST0_SYSTEM Position

MXC_F_GCR_RST0_TIMER0

#define MXC_F_GCR_RST0_TIMER0   ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER0_POS))

RST0_TIMER0 Mask

MXC_F_GCR_RST0_TIMER0_POS

#define MXC_F_GCR_RST0_TIMER0_POS   5

RST0_TIMER0 Position

MXC_F_GCR_RST0_TIMER1

#define MXC_F_GCR_RST0_TIMER1   ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER1_POS))

RST0_TIMER1 Mask

MXC_F_GCR_RST0_TIMER1_POS

#define MXC_F_GCR_RST0_TIMER1_POS   6

RST0_TIMER1 Position

MXC_F_GCR_RST0_TIMER2

#define MXC_F_GCR_RST0_TIMER2   ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TIMER2_POS))

RST0_TIMER2 Mask

MXC_F_GCR_RST0_TIMER2_POS

#define MXC_F_GCR_RST0_TIMER2_POS   7

RST0_TIMER2 Position

MXC_F_GCR_RST0_UART0

#define MXC_F_GCR_RST0_UART0   ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART0_POS))

RST0_UART0 Mask

MXC_F_GCR_RST0_UART0_POS

#define MXC_F_GCR_RST0_UART0_POS   11

RST0_UART0 Position

MXC_F_GCR_RST0_UART1

#define MXC_F_GCR_RST0_UART1   ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART1_POS))

RST0_UART1 Mask

MXC_F_GCR_RST0_UART1_POS

#define MXC_F_GCR_RST0_UART1_POS   12

RST0_UART1 Position

MXC_F_GCR_RST0_WDT0

#define MXC_F_GCR_RST0_WDT0   ((uint32_t)(0x1UL << MXC_F_GCR_RST0_WDT0_POS))

RST0_WDT0 Mask

MXC_F_GCR_RST0_WDT0_POS

#define MXC_F_GCR_RST0_WDT0_POS   1

RST0_WDT0 Position