SPIMSS_DMA

Macros
#define	MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS   0
#define	MXC_F_SPIMSS_DMA_TX_FIFO_LVL   ((uint32_t)(0x7UL << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS))
#define	MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRY1   ((uint32_t)0x0UL)
#define	MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRY1   (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRY1 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS)
#define	MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES2   ((uint32_t)0x1UL)
#define	MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES2   (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES2 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS)
#define	MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES3   ((uint32_t)0x2UL)
#define	MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES3   (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES3 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS)
#define	MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES4   ((uint32_t)0x3UL)
#define	MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES4   (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES4 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS)
#define	MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES5   ((uint32_t)0x4UL)
#define	MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES5   (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES5 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS)
#define	MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES6   ((uint32_t)0x5UL)
#define	MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES6   (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES6 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS)
#define	MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES7   ((uint32_t)0x6UL)
#define	MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES7   (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES7 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS)
#define	MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES8   ((uint32_t)0x7UL)
#define	MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES8   (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES8 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS)
#define	MXC_F_SPIMSS_DMA_TX_FIFO_CLR_POS   4
#define	MXC_F_SPIMSS_DMA_TX_FIFO_CLR   ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_TX_FIFO_CLR_POS))
#define	MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS   8
#define	MXC_F_SPIMSS_DMA_TX_FIFO_CNT   ((uint32_t)(0xFUL << MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS))
#define	MXC_F_SPIMSS_DMA_TX_DMA_EN_POS   15
#define	MXC_F_SPIMSS_DMA_TX_DMA_EN   ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_TX_DMA_EN_POS))
#define	MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS   16
#define	MXC_F_SPIMSS_DMA_RX_FIFO_LVL   ((uint32_t)(0x7UL << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS))
#define	MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRY1   ((uint32_t)0x0UL)
#define	MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRY1   (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRY1 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS)
#define	MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES2   ((uint32_t)0x1UL)
#define	MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES2   (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES2 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS)
#define	MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES3   ((uint32_t)0x2UL)
#define	MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES3   (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES3 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS)
#define	MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES4   ((uint32_t)0x3UL)
#define	MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES4   (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES4 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS)
#define	MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES5   ((uint32_t)0x4UL)
#define	MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES5   (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES5 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS)
#define	MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES6   ((uint32_t)0x5UL)
#define	MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES6   (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES6 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS)
#define	MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES7   ((uint32_t)0x6UL)
#define	MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES7   (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES7 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS)
#define	MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES8   ((uint32_t)0x7UL)
#define	MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES8   (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES8 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS)
#define	MXC_F_SPIMSS_DMA_RX_FIFO_CLR_POS   20
#define	MXC_F_SPIMSS_DMA_RX_FIFO_CLR   ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_RX_FIFO_CLR_POS))
#define	MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS   24
#define	MXC_F_SPIMSS_DMA_RX_FIFO_CNT   ((uint32_t)(0xFUL << MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS))
#define	MXC_F_SPIMSS_DMA_RX_DMA_EN_POS   31
#define	MXC_F_SPIMSS_DMA_RX_DMA_EN   ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_RX_DMA_EN_POS))

Detailed Description

SPI DMA Register.

Macro Definition Documentation

MXC_F_SPIMSS_DMA_RX_DMA_EN

#define MXC_F_SPIMSS_DMA_RX_DMA_EN   ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_RX_DMA_EN_POS))

DMA_RX_DMA_EN Mask

MXC_F_SPIMSS_DMA_RX_DMA_EN_POS

#define MXC_F_SPIMSS_DMA_RX_DMA_EN_POS   31

DMA_RX_DMA_EN Position

MXC_F_SPIMSS_DMA_RX_FIFO_CLR

#define MXC_F_SPIMSS_DMA_RX_FIFO_CLR   ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_RX_FIFO_CLR_POS))

DMA_RX_FIFO_CLR Mask

MXC_F_SPIMSS_DMA_RX_FIFO_CLR_POS

#define MXC_F_SPIMSS_DMA_RX_FIFO_CLR_POS   20

DMA_RX_FIFO_CLR Position

MXC_F_SPIMSS_DMA_RX_FIFO_CNT

#define MXC_F_SPIMSS_DMA_RX_FIFO_CNT   ((uint32_t)(0xFUL << MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS))

DMA_RX_FIFO_CNT Mask

MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS

#define MXC_F_SPIMSS_DMA_RX_FIFO_CNT_POS   24

DMA_RX_FIFO_CNT Position

MXC_F_SPIMSS_DMA_RX_FIFO_LVL

#define MXC_F_SPIMSS_DMA_RX_FIFO_LVL   ((uint32_t)(0x7UL << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS))

DMA_RX_FIFO_LVL Mask

MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS

#define MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS   16

DMA_RX_FIFO_LVL Position

MXC_F_SPIMSS_DMA_TX_DMA_EN

#define MXC_F_SPIMSS_DMA_TX_DMA_EN   ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_TX_DMA_EN_POS))

DMA_TX_DMA_EN Mask

MXC_F_SPIMSS_DMA_TX_DMA_EN_POS

#define MXC_F_SPIMSS_DMA_TX_DMA_EN_POS   15

DMA_TX_DMA_EN Position

MXC_F_SPIMSS_DMA_TX_FIFO_CLR

#define MXC_F_SPIMSS_DMA_TX_FIFO_CLR   ((uint32_t)(0x1UL << MXC_F_SPIMSS_DMA_TX_FIFO_CLR_POS))

DMA_TX_FIFO_CLR Mask

MXC_F_SPIMSS_DMA_TX_FIFO_CLR_POS

#define MXC_F_SPIMSS_DMA_TX_FIFO_CLR_POS   4

DMA_TX_FIFO_CLR Position

MXC_F_SPIMSS_DMA_TX_FIFO_CNT

#define MXC_F_SPIMSS_DMA_TX_FIFO_CNT   ((uint32_t)(0xFUL << MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS))

DMA_TX_FIFO_CNT Mask

MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS

#define MXC_F_SPIMSS_DMA_TX_FIFO_CNT_POS   8

DMA_TX_FIFO_CNT Position

MXC_F_SPIMSS_DMA_TX_FIFO_LVL

#define MXC_F_SPIMSS_DMA_TX_FIFO_LVL   ((uint32_t)(0x7UL << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS))

DMA_TX_FIFO_LVL Mask

MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS

#define MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS   0

DMA_TX_FIFO_LVL Position

MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES2

#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES2   (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES2 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS)

DMA_RX_FIFO_LVL_ENTRIES2 Setting

MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES3

#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES3   (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES3 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS)

DMA_RX_FIFO_LVL_ENTRIES3 Setting

MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES4

#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES4   (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES4 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS)

DMA_RX_FIFO_LVL_ENTRIES4 Setting

MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES5

#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES5   (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES5 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS)

DMA_RX_FIFO_LVL_ENTRIES5 Setting

MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES6

#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES6   (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES6 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS)

DMA_RX_FIFO_LVL_ENTRIES6 Setting

MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES7

#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES7   (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES7 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS)

DMA_RX_FIFO_LVL_ENTRIES7 Setting

MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES8

#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES8   (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES8 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS)

DMA_RX_FIFO_LVL_ENTRIES8 Setting

MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRY1

#define MXC_S_SPIMSS_DMA_RX_FIFO_LVL_ENTRY1   (MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRY1 << MXC_F_SPIMSS_DMA_RX_FIFO_LVL_POS)

DMA_RX_FIFO_LVL_ENTRY1 Setting

MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES2

#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES2   (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES2 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS)

DMA_TX_FIFO_LVL_ENTRIES2 Setting

MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES3

#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES3   (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES3 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS)

DMA_TX_FIFO_LVL_ENTRIES3 Setting

MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES4

#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES4   (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES4 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS)

DMA_TX_FIFO_LVL_ENTRIES4 Setting

MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES5

#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES5   (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES5 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS)

DMA_TX_FIFO_LVL_ENTRIES5 Setting

MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES6

#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES6   (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES6 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS)

DMA_TX_FIFO_LVL_ENTRIES6 Setting

MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES7

#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES7   (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES7 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS)

DMA_TX_FIFO_LVL_ENTRIES7 Setting

MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES8

#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES8   (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES8 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS)

DMA_TX_FIFO_LVL_ENTRIES8 Setting

MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRY1

#define MXC_S_SPIMSS_DMA_TX_FIFO_LVL_ENTRY1   (MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRY1 << MXC_F_SPIMSS_DMA_TX_FIFO_LVL_POS)

DMA_TX_FIFO_LVL_ENTRY1 Setting

MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES2

#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES2   ((uint32_t)0x1UL)

DMA_RX_FIFO_LVL_ENTRIES2 Value

MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES3

#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES3   ((uint32_t)0x2UL)

DMA_RX_FIFO_LVL_ENTRIES3 Value

MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES4

#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES4   ((uint32_t)0x3UL)

DMA_RX_FIFO_LVL_ENTRIES4 Value

MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES5

#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES5   ((uint32_t)0x4UL)

DMA_RX_FIFO_LVL_ENTRIES5 Value

MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES6

#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES6   ((uint32_t)0x5UL)

DMA_RX_FIFO_LVL_ENTRIES6 Value

MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES7

#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES7   ((uint32_t)0x6UL)

DMA_RX_FIFO_LVL_ENTRIES7 Value

MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES8

#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRIES8   ((uint32_t)0x7UL)

DMA_RX_FIFO_LVL_ENTRIES8 Value

MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRY1

#define MXC_V_SPIMSS_DMA_RX_FIFO_LVL_ENTRY1   ((uint32_t)0x0UL)

DMA_RX_FIFO_LVL_ENTRY1 Value

MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES2

#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES2   ((uint32_t)0x1UL)

DMA_TX_FIFO_LVL_ENTRIES2 Value

MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES3

#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES3   ((uint32_t)0x2UL)

DMA_TX_FIFO_LVL_ENTRIES3 Value

MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES4

#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES4   ((uint32_t)0x3UL)

DMA_TX_FIFO_LVL_ENTRIES4 Value

MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES5

#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES5   ((uint32_t)0x4UL)

DMA_TX_FIFO_LVL_ENTRIES5 Value

MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES6

#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES6   ((uint32_t)0x5UL)

DMA_TX_FIFO_LVL_ENTRIES6 Value

MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES7

#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES7   ((uint32_t)0x6UL)

DMA_TX_FIFO_LVL_ENTRIES7 Value

MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES8

#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRIES8   ((uint32_t)0x7UL)

DMA_TX_FIFO_LVL_ENTRIES8 Value

MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRY1

#define MXC_V_SPIMSS_DMA_TX_FIFO_LVL_ENTRY1   ((uint32_t)0x0UL)

DMA_TX_FIFO_LVL_ENTRY1 Value