MAX32660 Peripheral Driver API
Peripheral Driver API for the MAX32660
i2c_regs.h
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1
8/******************************************************************************
9 *
10 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by
11 * Analog Devices, Inc.),
12 * Copyright (C) 2023-2024 Analog Devices, Inc.
13 *
14 * Licensed under the Apache License, Version 2.0 (the "License");
15 * you may not use this file except in compliance with the License.
16 * You may obtain a copy of the License at
17 *
18 * http://www.apache.org/licenses/LICENSE-2.0
19 *
20 * Unless required by applicable law or agreed to in writing, software
21 * distributed under the License is distributed on an "AS IS" BASIS,
22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 * See the License for the specific language governing permissions and
24 * limitations under the License.
25 *
26 ******************************************************************************/
27
28#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_I2C_REGS_H_
29#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_I2C_REGS_H_
30
31/* **** Includes **** */
32#include <stdint.h>
33
34#ifdef __cplusplus
35extern "C" {
36#endif
37
38#if defined (__ICCARM__)
39 #pragma system_include
40#endif
41
42#if defined (__CC_ARM)
43 #pragma anon_unions
44#endif
46/*
47 If types are not defined elsewhere (CMSIS) define them here
48*/
49#ifndef __IO
50#define __IO volatile
51#endif
52#ifndef __I
53#define __I volatile const
54#endif
55#ifndef __O
56#define __O volatile
57#endif
58#ifndef __R
59#define __R volatile const
60#endif
62
63/* **** Definitions **** */
64
76typedef struct {
77 __IO uint32_t ctrl0;
78 __IO uint32_t status;
79 __IO uint32_t intfl0;
80 __IO uint32_t inten0;
81 __IO uint32_t intfl1;
82 __IO uint32_t inten1;
83 __IO uint32_t fifolen;
84 __IO uint32_t rxctrl0;
85 __IO uint32_t rxctrl1;
86 __IO uint32_t txctrl0;
87 __IO uint32_t txctrl1;
88 __IO uint32_t fifo;
89 __IO uint32_t mstr_mode;
90 __IO uint32_t clklo;
91 __IO uint32_t clkhi;
92 __IO uint32_t hs_clk;
93 __IO uint32_t timeout;
94 __IO uint32_t sladdr;
95 __IO uint32_t dma;
97
98/* Register offsets for module I2C */
105#define MXC_R_I2C_CTRL0 ((uint32_t)0x00000000UL)
106#define MXC_R_I2C_STATUS ((uint32_t)0x00000004UL)
107#define MXC_R_I2C_INTFL0 ((uint32_t)0x00000008UL)
108#define MXC_R_I2C_INTEN0 ((uint32_t)0x0000000CUL)
109#define MXC_R_I2C_INTFL1 ((uint32_t)0x00000010UL)
110#define MXC_R_I2C_INTEN1 ((uint32_t)0x00000014UL)
111#define MXC_R_I2C_FIFOLEN ((uint32_t)0x00000018UL)
112#define MXC_R_I2C_RXCTRL0 ((uint32_t)0x0000001CUL)
113#define MXC_R_I2C_RXCTRL1 ((uint32_t)0x00000020UL)
114#define MXC_R_I2C_TXCTRL0 ((uint32_t)0x00000024UL)
115#define MXC_R_I2C_TXCTRL1 ((uint32_t)0x00000028UL)
116#define MXC_R_I2C_FIFO ((uint32_t)0x0000002CUL)
117#define MXC_R_I2C_MSTR_MODE ((uint32_t)0x00000030UL)
118#define MXC_R_I2C_CLKLO ((uint32_t)0x00000034UL)
119#define MXC_R_I2C_CLKHI ((uint32_t)0x00000038UL)
120#define MXC_R_I2C_HS_CLK ((uint32_t)0x0000003CUL)
121#define MXC_R_I2C_TIMEOUT ((uint32_t)0x00000040UL)
122#define MXC_R_I2C_SLADDR ((uint32_t)0x00000044UL)
123#define MXC_R_I2C_DMA ((uint32_t)0x00000048UL)
132#define MXC_F_I2C_CTRL0_I2CEN_POS 0
133#define MXC_F_I2C_CTRL0_I2CEN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_I2CEN_POS))
135#define MXC_F_I2C_CTRL0_MST_POS 1
136#define MXC_F_I2C_CTRL0_MST ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_MST_POS))
138#define MXC_F_I2C_CTRL0_GCEN_POS 2
139#define MXC_F_I2C_CTRL0_GCEN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_GCEN_POS))
141#define MXC_F_I2C_CTRL0_IRXM_POS 3
142#define MXC_F_I2C_CTRL0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_IRXM_POS))
144#define MXC_F_I2C_CTRL0_ACK_POS 4
145#define MXC_F_I2C_CTRL0_ACK ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_ACK_POS))
147#define MXC_F_I2C_CTRL0_SCLO_POS 6
148#define MXC_F_I2C_CTRL0_SCLO ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCLO_POS))
150#define MXC_F_I2C_CTRL0_SDAO_POS 7
151#define MXC_F_I2C_CTRL0_SDAO ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SDAO_POS))
153#define MXC_F_I2C_CTRL0_SCL_POS 8
154#define MXC_F_I2C_CTRL0_SCL ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCL_POS))
156#define MXC_F_I2C_CTRL0_SDA_POS 9
157#define MXC_F_I2C_CTRL0_SDA ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SDA_POS))
159#define MXC_F_I2C_CTRL0_SWOE_POS 10
160#define MXC_F_I2C_CTRL0_SWOE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SWOE_POS))
162#define MXC_F_I2C_CTRL0_READ_POS 11
163#define MXC_F_I2C_CTRL0_READ ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_READ_POS))
165#define MXC_F_I2C_CTRL0_SCL_STRD_POS 12
166#define MXC_F_I2C_CTRL0_SCL_STRD ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCL_STRD_POS))
168#define MXC_F_I2C_CTRL0_SCL_PPM_POS 13
169#define MXC_F_I2C_CTRL0_SCL_PPM ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCL_PPM_POS))
171#define MXC_F_I2C_CTRL0_HSMODE_POS 15
172#define MXC_F_I2C_CTRL0_HSMODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_HSMODE_POS))
182#define MXC_F_I2C_STATUS_BUSY_POS 0
183#define MXC_F_I2C_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_BUSY_POS))
185#define MXC_F_I2C_STATUS_RXE_POS 1
186#define MXC_F_I2C_STATUS_RXE ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RXE_POS))
188#define MXC_F_I2C_STATUS_RXF_POS 2
189#define MXC_F_I2C_STATUS_RXF ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RXF_POS))
191#define MXC_F_I2C_STATUS_TXE_POS 3
192#define MXC_F_I2C_STATUS_TXE ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TXE_POS))
194#define MXC_F_I2C_STATUS_TXF_POS 4
195#define MXC_F_I2C_STATUS_TXF ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TXF_POS))
197#define MXC_F_I2C_STATUS_CKMD_POS 5
198#define MXC_F_I2C_STATUS_CKMD ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_CKMD_POS))
200#define MXC_F_I2C_STATUS_STAT_POS 8
201#define MXC_F_I2C_STATUS_STAT ((uint32_t)(0xFUL << MXC_F_I2C_STATUS_STAT_POS))
202#define MXC_V_I2C_STATUS_STAT_IDLE ((uint32_t)0x0UL)
203#define MXC_S_I2C_STATUS_STAT_IDLE (MXC_V_I2C_STATUS_STAT_IDLE << MXC_F_I2C_STATUS_STAT_POS)
204#define MXC_V_I2C_STATUS_STAT_MTX_ADDR ((uint32_t)0x1UL)
205#define MXC_S_I2C_STATUS_STAT_MTX_ADDR (MXC_V_I2C_STATUS_STAT_MTX_ADDR << MXC_F_I2C_STATUS_STAT_POS)
206#define MXC_V_I2C_STATUS_STAT_MRX_ADDR_ACK ((uint32_t)0x2UL)
207#define MXC_S_I2C_STATUS_STAT_MRX_ADDR_ACK (MXC_V_I2C_STATUS_STAT_MRX_ADDR_ACK << MXC_F_I2C_STATUS_STAT_POS)
208#define MXC_V_I2C_STATUS_STAT_MTX_EX_ADDR ((uint32_t)0x3UL)
209#define MXC_S_I2C_STATUS_STAT_MTX_EX_ADDR (MXC_V_I2C_STATUS_STAT_MTX_EX_ADDR << MXC_F_I2C_STATUS_STAT_POS)
210#define MXC_V_I2C_STATUS_STAT_MRX_EX_ADDR ((uint32_t)0x4UL)
211#define MXC_S_I2C_STATUS_STAT_MRX_EX_ADDR (MXC_V_I2C_STATUS_STAT_MRX_EX_ADDR << MXC_F_I2C_STATUS_STAT_POS)
212#define MXC_V_I2C_STATUS_STAT_SRX_ADDR ((uint32_t)0x5UL)
213#define MXC_S_I2C_STATUS_STAT_SRX_ADDR (MXC_V_I2C_STATUS_STAT_SRX_ADDR << MXC_F_I2C_STATUS_STAT_POS)
214#define MXC_V_I2C_STATUS_STAT_STX_ADDR_ACK ((uint32_t)0x6UL)
215#define MXC_S_I2C_STATUS_STAT_STX_ADDR_ACK (MXC_V_I2C_STATUS_STAT_STX_ADDR_ACK << MXC_F_I2C_STATUS_STAT_POS)
216#define MXC_V_I2C_STATUS_STAT_SRX_EX_ADDR ((uint32_t)0x7UL)
217#define MXC_S_I2C_STATUS_STAT_SRX_EX_ADDR (MXC_V_I2C_STATUS_STAT_SRX_EX_ADDR << MXC_F_I2C_STATUS_STAT_POS)
218#define MXC_V_I2C_STATUS_STAT_STX_EX_ADDR_ACK ((uint32_t)0x8UL)
219#define MXC_S_I2C_STATUS_STAT_STX_EX_ADDR_ACK (MXC_V_I2C_STATUS_STAT_STX_EX_ADDR_ACK << MXC_F_I2C_STATUS_STAT_POS)
220#define MXC_V_I2C_STATUS_STAT_TX ((uint32_t)0x9UL)
221#define MXC_S_I2C_STATUS_STAT_TX (MXC_V_I2C_STATUS_STAT_TX << MXC_F_I2C_STATUS_STAT_POS)
222#define MXC_V_I2C_STATUS_STAT_RX_ACK ((uint32_t)0xAUL)
223#define MXC_S_I2C_STATUS_STAT_RX_ACK (MXC_V_I2C_STATUS_STAT_RX_ACK << MXC_F_I2C_STATUS_STAT_POS)
224#define MXC_V_I2C_STATUS_STAT_RX ((uint32_t)0xBUL)
225#define MXC_S_I2C_STATUS_STAT_RX (MXC_V_I2C_STATUS_STAT_RX << MXC_F_I2C_STATUS_STAT_POS)
226#define MXC_V_I2C_STATUS_STAT_TX_ACK ((uint32_t)0xCUL)
227#define MXC_S_I2C_STATUS_STAT_TX_ACK (MXC_V_I2C_STATUS_STAT_TX_ACK << MXC_F_I2C_STATUS_STAT_POS)
228#define MXC_V_I2C_STATUS_STAT_NACK ((uint32_t)0xDUL)
229#define MXC_S_I2C_STATUS_STAT_NACK (MXC_V_I2C_STATUS_STAT_NACK << MXC_F_I2C_STATUS_STAT_POS)
230#define MXC_V_I2C_STATUS_STAT_BY_ST ((uint32_t)0xFUL)
231#define MXC_S_I2C_STATUS_STAT_BY_ST (MXC_V_I2C_STATUS_STAT_BY_ST << MXC_F_I2C_STATUS_STAT_POS)
241#define MXC_F_I2C_INTFL0_DONEI_POS 0
242#define MXC_F_I2C_INTFL0_DONEI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DONEI_POS))
244#define MXC_F_I2C_INTFL0_IRXMI_POS 1
245#define MXC_F_I2C_INTFL0_IRXMI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_IRXMI_POS))
247#define MXC_F_I2C_INTFL0_GCI_POS 2
248#define MXC_F_I2C_INTFL0_GCI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_GCI_POS))
250#define MXC_F_I2C_INTFL0_AMI_POS 3
251#define MXC_F_I2C_INTFL0_AMI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_AMI_POS))
253#define MXC_F_I2C_INTFL0_RXTHI_POS 4
254#define MXC_F_I2C_INTFL0_RXTHI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_RXTHI_POS))
256#define MXC_F_I2C_INTFL0_TXTHI_POS 5
257#define MXC_F_I2C_INTFL0_TXTHI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TXTHI_POS))
259#define MXC_F_I2C_INTFL0_STOPI_POS 6
260#define MXC_F_I2C_INTFL0_STOPI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STOPI_POS))
262#define MXC_F_I2C_INTFL0_ADRACKI_POS 7
263#define MXC_F_I2C_INTFL0_ADRACKI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADRACKI_POS))
265#define MXC_F_I2C_INTFL0_ARBERI_POS 8
266#define MXC_F_I2C_INTFL0_ARBERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ARBERI_POS))
268#define MXC_F_I2C_INTFL0_TOERI_POS 9
269#define MXC_F_I2C_INTFL0_TOERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TOERI_POS))
271#define MXC_F_I2C_INTFL0_ADRERI_POS 10
272#define MXC_F_I2C_INTFL0_ADRERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADRERI_POS))
274#define MXC_F_I2C_INTFL0_DATERI_POS 11
275#define MXC_F_I2C_INTFL0_DATERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DATERI_POS))
277#define MXC_F_I2C_INTFL0_DNRERI_POS 12
278#define MXC_F_I2C_INTFL0_DNRERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DNRERI_POS))
280#define MXC_F_I2C_INTFL0_STRTERI_POS 13
281#define MXC_F_I2C_INTFL0_STRTERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STRTERI_POS))
283#define MXC_F_I2C_INTFL0_STOPERI_POS 14
284#define MXC_F_I2C_INTFL0_STOPERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STOPERI_POS))
286#define MXC_F_I2C_INTFL0_TXLOI_POS 15
287#define MXC_F_I2C_INTFL0_TXLOI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TXLOI_POS))
289#define MXC_F_I2C_INTFL0_MAMI_POS 16
290#define MXC_F_I2C_INTFL0_MAMI ((uint32_t)(0xFUL << MXC_F_I2C_INTFL0_MAMI_POS))
300#define MXC_F_I2C_INTEN0_DONEIE_POS 0
301#define MXC_F_I2C_INTEN0_DONEIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DONEIE_POS))
303#define MXC_F_I2C_INTEN0_IRXMIE_POS 1
304#define MXC_F_I2C_INTEN0_IRXMIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_IRXMIE_POS))
306#define MXC_F_I2C_INTEN0_GCIE_POS 2
307#define MXC_F_I2C_INTEN0_GCIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_GCIE_POS))
309#define MXC_F_I2C_INTEN0_AMIE_POS 3
310#define MXC_F_I2C_INTEN0_AMIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_AMIE_POS))
312#define MXC_F_I2C_INTEN0_RXTHIE_POS 4
313#define MXC_F_I2C_INTEN0_RXTHIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_RXTHIE_POS))
315#define MXC_F_I2C_INTEN0_TXTHIE_POS 5
316#define MXC_F_I2C_INTEN0_TXTHIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TXTHIE_POS))
318#define MXC_F_I2C_INTEN0_STOPIE_POS 6
319#define MXC_F_I2C_INTEN0_STOPIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOPIE_POS))
321#define MXC_F_I2C_INTEN0_ADRACKIE_POS 7
322#define MXC_F_I2C_INTEN0_ADRACKIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADRACKIE_POS))
324#define MXC_F_I2C_INTEN0_ARBERIE_POS 8
325#define MXC_F_I2C_INTEN0_ARBERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ARBERIE_POS))
327#define MXC_F_I2C_INTEN0_TOERIE_POS 9
328#define MXC_F_I2C_INTEN0_TOERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TOERIE_POS))
330#define MXC_F_I2C_INTEN0_ADRERIE_POS 10
331#define MXC_F_I2C_INTEN0_ADRERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADRERIE_POS))
333#define MXC_F_I2C_INTEN0_DATERIE_POS 11
334#define MXC_F_I2C_INTEN0_DATERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DATERIE_POS))
336#define MXC_F_I2C_INTEN0_DNRERIE_POS 12
337#define MXC_F_I2C_INTEN0_DNRERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DNRERIE_POS))
339#define MXC_F_I2C_INTEN0_STRTERIE_POS 13
340#define MXC_F_I2C_INTEN0_STRTERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STRTERIE_POS))
342#define MXC_F_I2C_INTEN0_STOPERIE_POS 14
343#define MXC_F_I2C_INTEN0_STOPERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOPERIE_POS))
345#define MXC_F_I2C_INTEN0_TXLOIE_POS 15
346#define MXC_F_I2C_INTEN0_TXLOIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TXLOIE_POS))
348#define MXC_F_I2C_INTEN0_MAMIE_POS 16
349#define MXC_F_I2C_INTEN0_MAMIE ((uint32_t)(0xFUL << MXC_F_I2C_INTEN0_MAMIE_POS))
359#define MXC_F_I2C_INTFL1_RXOFI_POS 0
360#define MXC_F_I2C_INTFL1_RXOFI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_RXOFI_POS))
362#define MXC_F_I2C_INTFL1_TXUFI_POS 1
363#define MXC_F_I2C_INTFL1_TXUFI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_TXUFI_POS))
373#define MXC_F_I2C_INTEN1_RXOFIE_POS 0
374#define MXC_F_I2C_INTEN1_RXOFIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_RXOFIE_POS))
376#define MXC_F_I2C_INTEN1_TXUFIE_POS 1
377#define MXC_F_I2C_INTEN1_TXUFIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_TXUFIE_POS))
387#define MXC_F_I2C_FIFOLEN_RXLEN_POS 0
388#define MXC_F_I2C_FIFOLEN_RXLEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFOLEN_RXLEN_POS))
390#define MXC_F_I2C_FIFOLEN_TXLEN_POS 8
391#define MXC_F_I2C_FIFOLEN_TXLEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFOLEN_TXLEN_POS))
401#define MXC_F_I2C_RXCTRL0_DNR_POS 0
402#define MXC_F_I2C_RXCTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_RXCTRL0_DNR_POS))
404#define MXC_F_I2C_RXCTRL0_RXFSH_POS 7
405#define MXC_F_I2C_RXCTRL0_RXFSH ((uint32_t)(0x1UL << MXC_F_I2C_RXCTRL0_RXFSH_POS))
407#define MXC_F_I2C_RXCTRL0_RXTH_POS 8
408#define MXC_F_I2C_RXCTRL0_RXTH ((uint32_t)(0xFUL << MXC_F_I2C_RXCTRL0_RXTH_POS))
418#define MXC_F_I2C_RXCTRL1_RXCNT_POS 0
419#define MXC_F_I2C_RXCTRL1_RXCNT ((uint32_t)(0xFFUL << MXC_F_I2C_RXCTRL1_RXCNT_POS))
421#define MXC_F_I2C_RXCTRL1_RXFIFO_POS 8
422#define MXC_F_I2C_RXCTRL1_RXFIFO ((uint32_t)(0xFUL << MXC_F_I2C_RXCTRL1_RXFIFO_POS))
432#define MXC_F_I2C_TXCTRL0_TXPRELD_POS 0
433#define MXC_F_I2C_TXCTRL0_TXPRELD ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_TXPRELD_POS))
435#define MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS 1
436#define MXC_F_I2C_TXCTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS))
438#define MXC_F_I2C_TXCTRL0_TXFSH_POS 7
439#define MXC_F_I2C_TXCTRL0_TXFSH ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_TXFSH_POS))
441#define MXC_F_I2C_TXCTRL0_TXTH_POS 8
442#define MXC_F_I2C_TXCTRL0_TXTH ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL0_TXTH_POS))
452#define MXC_F_I2C_TXCTRL1_TXRDY_POS 0
453#define MXC_F_I2C_TXCTRL1_TXRDY ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_TXRDY_POS))
455#define MXC_F_I2C_TXCTRL1_TXLAST_POS 1
456#define MXC_F_I2C_TXCTRL1_TXLAST ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_TXLAST_POS))
458#define MXC_F_I2C_TXCTRL1_FLSH_GCADDR_DIS_POS 2
459#define MXC_F_I2C_TXCTRL1_FLSH_GCADDR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_FLSH_GCADDR_DIS_POS))
461#define MXC_F_I2C_TXCTRL1_FLSH_SLADDR_DIS_POS 4
462#define MXC_F_I2C_TXCTRL1_FLSH_SLADDR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_FLSH_SLADDR_DIS_POS))
464#define MXC_F_I2C_TXCTRL1_FLSH_NACK_DIS_POS 5
465#define MXC_F_I2C_TXCTRL1_FLSH_NACK_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_FLSH_NACK_DIS_POS))
467#define MXC_F_I2C_TXCTRL1_TXFIFO_POS 8
468#define MXC_F_I2C_TXCTRL1_TXFIFO ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL1_TXFIFO_POS))
478#define MXC_F_I2C_FIFO_DATA_POS 0
479#define MXC_F_I2C_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_DATA_POS))
489#define MXC_F_I2C_MSTR_MODE_START_POS 0
490#define MXC_F_I2C_MSTR_MODE_START ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_START_POS))
492#define MXC_F_I2C_MSTR_MODE_RESTART_POS 1
493#define MXC_F_I2C_MSTR_MODE_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_RESTART_POS))
495#define MXC_F_I2C_MSTR_MODE_STOP_POS 2
496#define MXC_F_I2C_MSTR_MODE_STOP ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_STOP_POS))
498#define MXC_F_I2C_MSTR_MODE_SEA_POS 7
499#define MXC_F_I2C_MSTR_MODE_SEA ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_SEA_POS))
509#define MXC_F_I2C_CLKLO_SCL_LO_POS 0
510#define MXC_F_I2C_CLKLO_SCL_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_CLKLO_SCL_LO_POS))
520#define MXC_F_I2C_CLKHI_SCL_HI_POS 0
521#define MXC_F_I2C_CLKHI_SCL_HI ((uint32_t)(0x1FFUL << MXC_F_I2C_CLKHI_SCL_HI_POS))
531#define MXC_F_I2C_HS_CLK_HS_CLK_LO_POS 0
532#define MXC_F_I2C_HS_CLK_HS_CLK_LO ((uint32_t)(0xFFUL << MXC_F_I2C_HS_CLK_HS_CLK_LO_POS))
534#define MXC_F_I2C_HS_CLK_HS_CLK_HI_POS 8
535#define MXC_F_I2C_HS_CLK_HS_CLK_HI ((uint32_t)(0xFFUL << MXC_F_I2C_HS_CLK_HS_CLK_HI_POS))
545#define MXC_F_I2C_TIMEOUT_TO_POS 0
546#define MXC_F_I2C_TIMEOUT_TO ((uint32_t)(0xFFFFUL << MXC_F_I2C_TIMEOUT_TO_POS))
556#define MXC_F_I2C_SLADDR_SLA_POS 0
557#define MXC_F_I2C_SLADDR_SLA ((uint32_t)(0x3FFUL << MXC_F_I2C_SLADDR_SLA_POS))
559#define MXC_F_I2C_SLADDR_SLADIS_POS 10
560#define MXC_F_I2C_SLADDR_SLADIS ((uint32_t)(0x1UL << MXC_F_I2C_SLADDR_SLADIS_POS))
562#define MXC_F_I2C_SLADDR_SLAIDX_POS 11
563#define MXC_F_I2C_SLADDR_SLAIDX ((uint32_t)(0xFUL << MXC_F_I2C_SLADDR_SLAIDX_POS))
565#define MXC_F_I2C_SLADDR_EA_POS 15
566#define MXC_F_I2C_SLADDR_EA ((uint32_t)(0x1UL << MXC_F_I2C_SLADDR_EA_POS))
576#define MXC_F_I2C_DMA_TXEN_POS 0
577#define MXC_F_I2C_DMA_TXEN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_TXEN_POS))
579#define MXC_F_I2C_DMA_RXEN_POS 1
580#define MXC_F_I2C_DMA_RXEN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_RXEN_POS))
584#ifdef __cplusplus
585}
586#endif
587
588#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_I2C_REGS_H_
__IO uint32_t ctrl0
Definition: i2c_regs.h:77
__IO uint32_t intfl0
Definition: i2c_regs.h:79
__IO uint32_t txctrl1
Definition: i2c_regs.h:87
__IO uint32_t inten0
Definition: i2c_regs.h:80
__IO uint32_t clklo
Definition: i2c_regs.h:90
__IO uint32_t rxctrl1
Definition: i2c_regs.h:85
__IO uint32_t timeout
Definition: i2c_regs.h:93
__IO uint32_t sladdr
Definition: i2c_regs.h:94
__IO uint32_t txctrl0
Definition: i2c_regs.h:86
__IO uint32_t clkhi
Definition: i2c_regs.h:91
__IO uint32_t inten1
Definition: i2c_regs.h:82
__IO uint32_t fifolen
Definition: i2c_regs.h:83
__IO uint32_t dma
Definition: i2c_regs.h:95
__IO uint32_t hs_clk
Definition: i2c_regs.h:92
__IO uint32_t fifo
Definition: i2c_regs.h:88
__IO uint32_t intfl1
Definition: i2c_regs.h:81
__IO uint32_t status
Definition: i2c_regs.h:78
__IO uint32_t rxctrl0
Definition: i2c_regs.h:84
__IO uint32_t mstr_mode
Definition: i2c_regs.h:89
Definition: i2c_regs.h:76