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#define | MXC_R_I2C_CTRL0 ((uint32_t)0x00000000UL) |
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#define | MXC_R_I2C_STATUS ((uint32_t)0x00000004UL) |
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#define | MXC_R_I2C_INTFL0 ((uint32_t)0x00000008UL) |
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#define | MXC_R_I2C_INTEN0 ((uint32_t)0x0000000CUL) |
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#define | MXC_R_I2C_INTFL1 ((uint32_t)0x00000010UL) |
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#define | MXC_R_I2C_INTEN1 ((uint32_t)0x00000014UL) |
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#define | MXC_R_I2C_FIFOLEN ((uint32_t)0x00000018UL) |
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#define | MXC_R_I2C_RXCTRL0 ((uint32_t)0x0000001CUL) |
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#define | MXC_R_I2C_RXCTRL1 ((uint32_t)0x00000020UL) |
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#define | MXC_R_I2C_TXCTRL0 ((uint32_t)0x00000024UL) |
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#define | MXC_R_I2C_TXCTRL1 ((uint32_t)0x00000028UL) |
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#define | MXC_R_I2C_FIFO ((uint32_t)0x0000002CUL) |
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#define | MXC_R_I2C_MSTR_MODE ((uint32_t)0x00000030UL) |
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#define | MXC_R_I2C_CLKLO ((uint32_t)0x00000034UL) |
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#define | MXC_R_I2C_CLKHI ((uint32_t)0x00000038UL) |
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#define | MXC_R_I2C_HS_CLK ((uint32_t)0x0000003CUL) |
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#define | MXC_R_I2C_TIMEOUT ((uint32_t)0x00000040UL) |
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#define | MXC_R_I2C_SLADDR ((uint32_t)0x00000044UL) |
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#define | MXC_R_I2C_DMA ((uint32_t)0x00000048UL) |
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#define | MXC_F_I2C_CTRL0_I2CEN_POS 0 |
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#define | MXC_F_I2C_CTRL0_I2CEN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_I2CEN_POS)) |
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#define | MXC_F_I2C_CTRL0_MST_POS 1 |
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#define | MXC_F_I2C_CTRL0_MST ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_MST_POS)) |
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#define | MXC_F_I2C_CTRL0_GCEN_POS 2 |
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#define | MXC_F_I2C_CTRL0_GCEN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_GCEN_POS)) |
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#define | MXC_F_I2C_CTRL0_IRXM_POS 3 |
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#define | MXC_F_I2C_CTRL0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_IRXM_POS)) |
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#define | MXC_F_I2C_CTRL0_ACK_POS 4 |
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#define | MXC_F_I2C_CTRL0_ACK ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_ACK_POS)) |
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#define | MXC_F_I2C_CTRL0_SCLO_POS 6 |
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#define | MXC_F_I2C_CTRL0_SCLO ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCLO_POS)) |
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#define | MXC_F_I2C_CTRL0_SDAO_POS 7 |
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#define | MXC_F_I2C_CTRL0_SDAO ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SDAO_POS)) |
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#define | MXC_F_I2C_CTRL0_SCL_POS 8 |
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#define | MXC_F_I2C_CTRL0_SCL ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCL_POS)) |
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#define | MXC_F_I2C_CTRL0_SDA_POS 9 |
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#define | MXC_F_I2C_CTRL0_SDA ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SDA_POS)) |
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#define | MXC_F_I2C_CTRL0_SWOE_POS 10 |
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#define | MXC_F_I2C_CTRL0_SWOE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SWOE_POS)) |
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#define | MXC_F_I2C_CTRL0_READ_POS 11 |
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#define | MXC_F_I2C_CTRL0_READ ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_READ_POS)) |
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#define | MXC_F_I2C_CTRL0_SCL_STRD_POS 12 |
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#define | MXC_F_I2C_CTRL0_SCL_STRD ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCL_STRD_POS)) |
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#define | MXC_F_I2C_CTRL0_SCL_PPM_POS 13 |
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#define | MXC_F_I2C_CTRL0_SCL_PPM ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_SCL_PPM_POS)) |
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#define | MXC_F_I2C_CTRL0_HSMODE_POS 15 |
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#define | MXC_F_I2C_CTRL0_HSMODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL0_HSMODE_POS)) |
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#define | MXC_F_I2C_STATUS_BUSY_POS 0 |
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#define | MXC_F_I2C_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_BUSY_POS)) |
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#define | MXC_F_I2C_STATUS_RXE_POS 1 |
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#define | MXC_F_I2C_STATUS_RXE ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RXE_POS)) |
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#define | MXC_F_I2C_STATUS_RXF_POS 2 |
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#define | MXC_F_I2C_STATUS_RXF ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RXF_POS)) |
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#define | MXC_F_I2C_STATUS_TXE_POS 3 |
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#define | MXC_F_I2C_STATUS_TXE ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TXE_POS)) |
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#define | MXC_F_I2C_STATUS_TXF_POS 4 |
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#define | MXC_F_I2C_STATUS_TXF ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TXF_POS)) |
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#define | MXC_F_I2C_STATUS_CKMD_POS 5 |
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#define | MXC_F_I2C_STATUS_CKMD ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_CKMD_POS)) |
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#define | MXC_F_I2C_STATUS_STAT_POS 8 |
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#define | MXC_F_I2C_STATUS_STAT ((uint32_t)(0xFUL << MXC_F_I2C_STATUS_STAT_POS)) |
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#define | MXC_V_I2C_STATUS_STAT_IDLE ((uint32_t)0x0UL) |
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#define | MXC_S_I2C_STATUS_STAT_IDLE (MXC_V_I2C_STATUS_STAT_IDLE << MXC_F_I2C_STATUS_STAT_POS) |
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#define | MXC_V_I2C_STATUS_STAT_MTX_ADDR ((uint32_t)0x1UL) |
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#define | MXC_S_I2C_STATUS_STAT_MTX_ADDR (MXC_V_I2C_STATUS_STAT_MTX_ADDR << MXC_F_I2C_STATUS_STAT_POS) |
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#define | MXC_V_I2C_STATUS_STAT_MRX_ADDR_ACK ((uint32_t)0x2UL) |
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#define | MXC_S_I2C_STATUS_STAT_MRX_ADDR_ACK (MXC_V_I2C_STATUS_STAT_MRX_ADDR_ACK << MXC_F_I2C_STATUS_STAT_POS) |
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#define | MXC_V_I2C_STATUS_STAT_MTX_EX_ADDR ((uint32_t)0x3UL) |
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#define | MXC_S_I2C_STATUS_STAT_MTX_EX_ADDR (MXC_V_I2C_STATUS_STAT_MTX_EX_ADDR << MXC_F_I2C_STATUS_STAT_POS) |
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#define | MXC_V_I2C_STATUS_STAT_MRX_EX_ADDR ((uint32_t)0x4UL) |
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#define | MXC_S_I2C_STATUS_STAT_MRX_EX_ADDR (MXC_V_I2C_STATUS_STAT_MRX_EX_ADDR << MXC_F_I2C_STATUS_STAT_POS) |
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#define | MXC_V_I2C_STATUS_STAT_SRX_ADDR ((uint32_t)0x5UL) |
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#define | MXC_S_I2C_STATUS_STAT_SRX_ADDR (MXC_V_I2C_STATUS_STAT_SRX_ADDR << MXC_F_I2C_STATUS_STAT_POS) |
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#define | MXC_V_I2C_STATUS_STAT_STX_ADDR_ACK ((uint32_t)0x6UL) |
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#define | MXC_S_I2C_STATUS_STAT_STX_ADDR_ACK (MXC_V_I2C_STATUS_STAT_STX_ADDR_ACK << MXC_F_I2C_STATUS_STAT_POS) |
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#define | MXC_V_I2C_STATUS_STAT_SRX_EX_ADDR ((uint32_t)0x7UL) |
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#define | MXC_S_I2C_STATUS_STAT_SRX_EX_ADDR (MXC_V_I2C_STATUS_STAT_SRX_EX_ADDR << MXC_F_I2C_STATUS_STAT_POS) |
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#define | MXC_V_I2C_STATUS_STAT_STX_EX_ADDR_ACK ((uint32_t)0x8UL) |
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#define | MXC_S_I2C_STATUS_STAT_STX_EX_ADDR_ACK (MXC_V_I2C_STATUS_STAT_STX_EX_ADDR_ACK << MXC_F_I2C_STATUS_STAT_POS) |
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#define | MXC_V_I2C_STATUS_STAT_TX ((uint32_t)0x9UL) |
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#define | MXC_S_I2C_STATUS_STAT_TX (MXC_V_I2C_STATUS_STAT_TX << MXC_F_I2C_STATUS_STAT_POS) |
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#define | MXC_V_I2C_STATUS_STAT_RX_ACK ((uint32_t)0xAUL) |
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#define | MXC_S_I2C_STATUS_STAT_RX_ACK (MXC_V_I2C_STATUS_STAT_RX_ACK << MXC_F_I2C_STATUS_STAT_POS) |
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#define | MXC_V_I2C_STATUS_STAT_RX ((uint32_t)0xBUL) |
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#define | MXC_S_I2C_STATUS_STAT_RX (MXC_V_I2C_STATUS_STAT_RX << MXC_F_I2C_STATUS_STAT_POS) |
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#define | MXC_V_I2C_STATUS_STAT_TX_ACK ((uint32_t)0xCUL) |
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#define | MXC_S_I2C_STATUS_STAT_TX_ACK (MXC_V_I2C_STATUS_STAT_TX_ACK << MXC_F_I2C_STATUS_STAT_POS) |
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#define | MXC_V_I2C_STATUS_STAT_NACK ((uint32_t)0xDUL) |
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#define | MXC_S_I2C_STATUS_STAT_NACK (MXC_V_I2C_STATUS_STAT_NACK << MXC_F_I2C_STATUS_STAT_POS) |
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#define | MXC_V_I2C_STATUS_STAT_BY_ST ((uint32_t)0xFUL) |
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#define | MXC_S_I2C_STATUS_STAT_BY_ST (MXC_V_I2C_STATUS_STAT_BY_ST << MXC_F_I2C_STATUS_STAT_POS) |
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#define | MXC_F_I2C_INTFL0_DONEI_POS 0 |
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#define | MXC_F_I2C_INTFL0_DONEI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DONEI_POS)) |
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#define | MXC_F_I2C_INTFL0_IRXMI_POS 1 |
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#define | MXC_F_I2C_INTFL0_IRXMI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_IRXMI_POS)) |
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#define | MXC_F_I2C_INTFL0_GCI_POS 2 |
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#define | MXC_F_I2C_INTFL0_GCI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_GCI_POS)) |
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#define | MXC_F_I2C_INTFL0_AMI_POS 3 |
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#define | MXC_F_I2C_INTFL0_AMI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_AMI_POS)) |
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#define | MXC_F_I2C_INTFL0_RXTHI_POS 4 |
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#define | MXC_F_I2C_INTFL0_RXTHI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_RXTHI_POS)) |
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#define | MXC_F_I2C_INTFL0_TXTHI_POS 5 |
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#define | MXC_F_I2C_INTFL0_TXTHI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TXTHI_POS)) |
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#define | MXC_F_I2C_INTFL0_STOPI_POS 6 |
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#define | MXC_F_I2C_INTFL0_STOPI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STOPI_POS)) |
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#define | MXC_F_I2C_INTFL0_ADRACKI_POS 7 |
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#define | MXC_F_I2C_INTFL0_ADRACKI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADRACKI_POS)) |
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#define | MXC_F_I2C_INTFL0_ARBERI_POS 8 |
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#define | MXC_F_I2C_INTFL0_ARBERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ARBERI_POS)) |
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#define | MXC_F_I2C_INTFL0_TOERI_POS 9 |
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#define | MXC_F_I2C_INTFL0_TOERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TOERI_POS)) |
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#define | MXC_F_I2C_INTFL0_ADRERI_POS 10 |
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#define | MXC_F_I2C_INTFL0_ADRERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADRERI_POS)) |
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#define | MXC_F_I2C_INTFL0_DATERI_POS 11 |
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#define | MXC_F_I2C_INTFL0_DATERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DATERI_POS)) |
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#define | MXC_F_I2C_INTFL0_DNRERI_POS 12 |
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#define | MXC_F_I2C_INTFL0_DNRERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DNRERI_POS)) |
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#define | MXC_F_I2C_INTFL0_STRTERI_POS 13 |
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#define | MXC_F_I2C_INTFL0_STRTERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STRTERI_POS)) |
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#define | MXC_F_I2C_INTFL0_STOPERI_POS 14 |
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#define | MXC_F_I2C_INTFL0_STOPERI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STOPERI_POS)) |
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#define | MXC_F_I2C_INTFL0_TXLOI_POS 15 |
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#define | MXC_F_I2C_INTFL0_TXLOI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TXLOI_POS)) |
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#define | MXC_F_I2C_INTFL0_MAMI_POS 16 |
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#define | MXC_F_I2C_INTFL0_MAMI ((uint32_t)(0xFUL << MXC_F_I2C_INTFL0_MAMI_POS)) |
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#define | MXC_F_I2C_INTEN0_DONEIE_POS 0 |
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#define | MXC_F_I2C_INTEN0_DONEIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DONEIE_POS)) |
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#define | MXC_F_I2C_INTEN0_IRXMIE_POS 1 |
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#define | MXC_F_I2C_INTEN0_IRXMIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_IRXMIE_POS)) |
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#define | MXC_F_I2C_INTEN0_GCIE_POS 2 |
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#define | MXC_F_I2C_INTEN0_GCIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_GCIE_POS)) |
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#define | MXC_F_I2C_INTEN0_AMIE_POS 3 |
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#define | MXC_F_I2C_INTEN0_AMIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_AMIE_POS)) |
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#define | MXC_F_I2C_INTEN0_RXTHIE_POS 4 |
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#define | MXC_F_I2C_INTEN0_RXTHIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_RXTHIE_POS)) |
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#define | MXC_F_I2C_INTEN0_TXTHIE_POS 5 |
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#define | MXC_F_I2C_INTEN0_TXTHIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TXTHIE_POS)) |
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#define | MXC_F_I2C_INTEN0_STOPIE_POS 6 |
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#define | MXC_F_I2C_INTEN0_STOPIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOPIE_POS)) |
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#define | MXC_F_I2C_INTEN0_ADRACKIE_POS 7 |
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#define | MXC_F_I2C_INTEN0_ADRACKIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADRACKIE_POS)) |
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#define | MXC_F_I2C_INTEN0_ARBERIE_POS 8 |
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#define | MXC_F_I2C_INTEN0_ARBERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ARBERIE_POS)) |
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#define | MXC_F_I2C_INTEN0_TOERIE_POS 9 |
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#define | MXC_F_I2C_INTEN0_TOERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TOERIE_POS)) |
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#define | MXC_F_I2C_INTEN0_ADRERIE_POS 10 |
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#define | MXC_F_I2C_INTEN0_ADRERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADRERIE_POS)) |
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#define | MXC_F_I2C_INTEN0_DATERIE_POS 11 |
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#define | MXC_F_I2C_INTEN0_DATERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DATERIE_POS)) |
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#define | MXC_F_I2C_INTEN0_DNRERIE_POS 12 |
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#define | MXC_F_I2C_INTEN0_DNRERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DNRERIE_POS)) |
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#define | MXC_F_I2C_INTEN0_STRTERIE_POS 13 |
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#define | MXC_F_I2C_INTEN0_STRTERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STRTERIE_POS)) |
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#define | MXC_F_I2C_INTEN0_STOPERIE_POS 14 |
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#define | MXC_F_I2C_INTEN0_STOPERIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOPERIE_POS)) |
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#define | MXC_F_I2C_INTEN0_TXLOIE_POS 15 |
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#define | MXC_F_I2C_INTEN0_TXLOIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TXLOIE_POS)) |
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#define | MXC_F_I2C_INTEN0_MAMIE_POS 16 |
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#define | MXC_F_I2C_INTEN0_MAMIE ((uint32_t)(0xFUL << MXC_F_I2C_INTEN0_MAMIE_POS)) |
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#define | MXC_F_I2C_INTFL1_RXOFI_POS 0 |
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#define | MXC_F_I2C_INTFL1_RXOFI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_RXOFI_POS)) |
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#define | MXC_F_I2C_INTFL1_TXUFI_POS 1 |
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#define | MXC_F_I2C_INTFL1_TXUFI ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_TXUFI_POS)) |
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#define | MXC_F_I2C_INTEN1_RXOFIE_POS 0 |
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#define | MXC_F_I2C_INTEN1_RXOFIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_RXOFIE_POS)) |
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#define | MXC_F_I2C_INTEN1_TXUFIE_POS 1 |
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#define | MXC_F_I2C_INTEN1_TXUFIE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_TXUFIE_POS)) |
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#define | MXC_F_I2C_FIFOLEN_RXLEN_POS 0 |
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#define | MXC_F_I2C_FIFOLEN_RXLEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFOLEN_RXLEN_POS)) |
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#define | MXC_F_I2C_FIFOLEN_TXLEN_POS 8 |
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#define | MXC_F_I2C_FIFOLEN_TXLEN ((uint32_t)(0xFFUL << MXC_F_I2C_FIFOLEN_TXLEN_POS)) |
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#define | MXC_F_I2C_RXCTRL0_DNR_POS 0 |
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#define | MXC_F_I2C_RXCTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_RXCTRL0_DNR_POS)) |
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#define | MXC_F_I2C_RXCTRL0_RXFSH_POS 7 |
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#define | MXC_F_I2C_RXCTRL0_RXFSH ((uint32_t)(0x1UL << MXC_F_I2C_RXCTRL0_RXFSH_POS)) |
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#define | MXC_F_I2C_RXCTRL0_RXTH_POS 8 |
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#define | MXC_F_I2C_RXCTRL0_RXTH ((uint32_t)(0xFUL << MXC_F_I2C_RXCTRL0_RXTH_POS)) |
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#define | MXC_F_I2C_RXCTRL1_RXCNT_POS 0 |
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#define | MXC_F_I2C_RXCTRL1_RXCNT ((uint32_t)(0xFFUL << MXC_F_I2C_RXCTRL1_RXCNT_POS)) |
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#define | MXC_F_I2C_RXCTRL1_RXFIFO_POS 8 |
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#define | MXC_F_I2C_RXCTRL1_RXFIFO ((uint32_t)(0xFUL << MXC_F_I2C_RXCTRL1_RXFIFO_POS)) |
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#define | MXC_F_I2C_TXCTRL0_TXPRELD_POS 0 |
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#define | MXC_F_I2C_TXCTRL0_TXPRELD ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_TXPRELD_POS)) |
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#define | MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS 1 |
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#define | MXC_F_I2C_TXCTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS)) |
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#define | MXC_F_I2C_TXCTRL0_TXFSH_POS 7 |
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#define | MXC_F_I2C_TXCTRL0_TXFSH ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_TXFSH_POS)) |
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#define | MXC_F_I2C_TXCTRL0_TXTH_POS 8 |
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#define | MXC_F_I2C_TXCTRL0_TXTH ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL0_TXTH_POS)) |
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#define | MXC_F_I2C_TXCTRL1_TXRDY_POS 0 |
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#define | MXC_F_I2C_TXCTRL1_TXRDY ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_TXRDY_POS)) |
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#define | MXC_F_I2C_TXCTRL1_TXLAST_POS 1 |
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#define | MXC_F_I2C_TXCTRL1_TXLAST ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_TXLAST_POS)) |
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#define | MXC_F_I2C_TXCTRL1_FLSH_GCADDR_DIS_POS 2 |
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#define | MXC_F_I2C_TXCTRL1_FLSH_GCADDR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_FLSH_GCADDR_DIS_POS)) |
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#define | MXC_F_I2C_TXCTRL1_FLSH_SLADDR_DIS_POS 4 |
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#define | MXC_F_I2C_TXCTRL1_FLSH_SLADDR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_FLSH_SLADDR_DIS_POS)) |
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#define | MXC_F_I2C_TXCTRL1_FLSH_NACK_DIS_POS 5 |
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#define | MXC_F_I2C_TXCTRL1_FLSH_NACK_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_FLSH_NACK_DIS_POS)) |
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#define | MXC_F_I2C_TXCTRL1_TXFIFO_POS 8 |
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#define | MXC_F_I2C_TXCTRL1_TXFIFO ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL1_TXFIFO_POS)) |
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#define | MXC_F_I2C_FIFO_DATA_POS 0 |
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#define | MXC_F_I2C_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_DATA_POS)) |
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#define | MXC_F_I2C_MSTR_MODE_START_POS 0 |
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#define | MXC_F_I2C_MSTR_MODE_START ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_START_POS)) |
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#define | MXC_F_I2C_MSTR_MODE_RESTART_POS 1 |
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#define | MXC_F_I2C_MSTR_MODE_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_RESTART_POS)) |
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#define | MXC_F_I2C_MSTR_MODE_STOP_POS 2 |
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#define | MXC_F_I2C_MSTR_MODE_STOP ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_STOP_POS)) |
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#define | MXC_F_I2C_MSTR_MODE_SEA_POS 7 |
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#define | MXC_F_I2C_MSTR_MODE_SEA ((uint32_t)(0x1UL << MXC_F_I2C_MSTR_MODE_SEA_POS)) |
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#define | MXC_F_I2C_CLKLO_SCL_LO_POS 0 |
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#define | MXC_F_I2C_CLKLO_SCL_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_CLKLO_SCL_LO_POS)) |
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#define | MXC_F_I2C_CLKHI_SCL_HI_POS 0 |
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#define | MXC_F_I2C_CLKHI_SCL_HI ((uint32_t)(0x1FFUL << MXC_F_I2C_CLKHI_SCL_HI_POS)) |
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#define | MXC_F_I2C_HS_CLK_HS_CLK_LO_POS 0 |
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#define | MXC_F_I2C_HS_CLK_HS_CLK_LO ((uint32_t)(0xFFUL << MXC_F_I2C_HS_CLK_HS_CLK_LO_POS)) |
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#define | MXC_F_I2C_HS_CLK_HS_CLK_HI_POS 8 |
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#define | MXC_F_I2C_HS_CLK_HS_CLK_HI ((uint32_t)(0xFFUL << MXC_F_I2C_HS_CLK_HS_CLK_HI_POS)) |
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#define | MXC_F_I2C_TIMEOUT_TO_POS 0 |
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#define | MXC_F_I2C_TIMEOUT_TO ((uint32_t)(0xFFFFUL << MXC_F_I2C_TIMEOUT_TO_POS)) |
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#define | MXC_F_I2C_SLADDR_SLA_POS 0 |
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#define | MXC_F_I2C_SLADDR_SLA ((uint32_t)(0x3FFUL << MXC_F_I2C_SLADDR_SLA_POS)) |
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#define | MXC_F_I2C_SLADDR_SLADIS_POS 10 |
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#define | MXC_F_I2C_SLADDR_SLADIS ((uint32_t)(0x1UL << MXC_F_I2C_SLADDR_SLADIS_POS)) |
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#define | MXC_F_I2C_SLADDR_SLAIDX_POS 11 |
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#define | MXC_F_I2C_SLADDR_SLAIDX ((uint32_t)(0xFUL << MXC_F_I2C_SLADDR_SLAIDX_POS)) |
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#define | MXC_F_I2C_SLADDR_EA_POS 15 |
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#define | MXC_F_I2C_SLADDR_EA ((uint32_t)(0x1UL << MXC_F_I2C_SLADDR_EA_POS)) |
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#define | MXC_F_I2C_DMA_TXEN_POS 0 |
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#define | MXC_F_I2C_DMA_TXEN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_TXEN_POS)) |
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#define | MXC_F_I2C_DMA_RXEN_POS 1 |
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#define | MXC_F_I2C_DMA_RXEN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_RXEN_POS)) |
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