mxc_sys.h

 
/******************************************************************************
 *
 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 
 * Analog Devices, Inc.),
 * Copyright (C) 2023-2024 Analog Devices, Inc.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 ******************************************************************************/
 
#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_SYS_H_
#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_SYS_H_
 
#include "mxc_device.h"
#include "gcr_regs.h"
 
#ifdef __cplusplus
extern "C" {
#endif
 
typedef enum {
    MXC_SYS_RESET0_DMA = MXC_F_GCR_RST0_DMA_POS, 
    MXC_SYS_RESET0_WDT0 = MXC_F_GCR_RST0_WDT0_POS, 
    MXC_SYS_RESET0_GPIO0 = MXC_F_GCR_RST0_GPIO0_POS, 
    MXC_SYS_RESET0_TIMER0 = MXC_F_GCR_RST0_TIMER0_POS, 
    MXC_SYS_RESET0_TIMER1 = MXC_F_GCR_RST0_TIMER1_POS, 
    MXC_SYS_RESET0_TIMER2 = MXC_F_GCR_RST0_TIMER2_POS, 
    MXC_SYS_RESET0_UART0 = MXC_F_GCR_RST0_UART0_POS, 
    MXC_SYS_RESET0_UART1 = MXC_F_GCR_RST0_UART1_POS, 
    MXC_SYS_RESET0_SPI0 = MXC_F_GCR_RST0_SPI0_POS, 
    MXC_SYS_RESET0_SPI1 = MXC_F_GCR_RST0_SPI1_POS, 
    MXC_SYS_RESET0_I2C0 = MXC_F_GCR_RST0_I2C0_POS, 
    MXC_SYS_RESET0_RTC = MXC_F_GCR_RST0_RTC_POS, 
    MXC_SYS_RESET0_SRST = MXC_F_GCR_RST0_SOFT_POS, 
    MXC_SYS_RESET0_PRST = MXC_F_GCR_RST0_PERIPH_POS, 
    MXC_SYS_RESET0_SYSTEM = MXC_F_GCR_RST0_SYSTEM_POS, 
    /* RESET1 Below this line we add 32 to separate RESET0 and RESET1 */
    MXC_SYS_RESET1_I2C1 = (MXC_F_GCR_RST1_I2C1_POS + 32), 
} mxc_sys_reset_t;
 
typedef enum {
    MXC_SYS_PERIPH_CLOCK_GPIO0 =
        MXC_F_GCR_PCLK_DIS0_GPIO0D_POS, 
    MXC_SYS_PERIPH_CLOCK_DMA =
        MXC_F_GCR_PCLK_DIS0_DMAD_POS, 
    MXC_SYS_PERIPH_CLOCK_SPI0 =
        MXC_F_GCR_PCLK_DIS0_SPI0D_POS, 
    MXC_SYS_PERIPH_CLOCK_SPI1 =
        MXC_F_GCR_PCLK_DIS0_SPI1D_POS, 
    MXC_SYS_PERIPH_CLOCK_UART0 =
        MXC_F_GCR_PCLK_DIS0_UART0D_POS, 
    MXC_SYS_PERIPH_CLOCK_UART1 =
        MXC_F_GCR_PCLK_DIS0_UART1D_POS, 
    MXC_SYS_PERIPH_CLOCK_I2C0 =
        MXC_F_GCR_PCLK_DIS0_I2C0D_POS, 
    MXC_SYS_PERIPH_CLOCK_TMR0 =
        MXC_F_GCR_PCLK_DIS0_TIMER0D_POS, 
    MXC_SYS_PERIPH_CLOCK_TMR1 =
        MXC_F_GCR_PCLK_DIS0_TIMER1D_POS, 
    MXC_SYS_PERIPH_CLOCK_TMR2 =
        MXC_F_GCR_PCLK_DIS0_TIMER2D_POS, 
    MXC_SYS_PERIPH_CLOCK_I2C1 =
        MXC_F_GCR_PCLK_DIS0_I2C1D_POS, 
    /* PCLKDIS1 Below this line we add 32 to separate PCLKDIS0 and PCLKDIS1 */
    MXC_SYS_PERIPH_CLOCK_FLCD =
        (MXC_F_GCR_PCLK_DIS1_FLCD_POS + 32), 
    MXC_SYS_PERIPH_CLOCK_ICACHE =
        (MXC_F_GCR_PCLK_DIS1_ICCD_POS + 32), 
} mxc_sys_periph_clock_t;
 
typedef enum {
    MXC_SYS_CLOCK_NANORING = MXC_V_GCR_CLK_CTRL_CLKSEL_NANORING, 
    MXC_SYS_CLOCK_HFXIN = MXC_V_GCR_CLK_CTRL_CLKSEL_HFXIN, 
    MXC_SYS_CLOCK_HFXIN_DIGITAL = 0x9, 
    MXC_SYS_CLOCK_HIRC = MXC_V_GCR_CLK_CTRL_CLKSEL_HIRC, 
} mxc_sys_system_clock_t;
 
typedef enum {
    MXC_SYS_CLOCK_DIV_1 = MXC_S_GCR_CLK_CTRL_PSC_DIV1,
    MXC_SYS_CLOCK_DIV_2 = MXC_S_GCR_CLK_CTRL_PSC_DIV2,
    MXC_SYS_CLOCK_DIV_4 = MXC_S_GCR_CLK_CTRL_PSC_DIV4,
    MXC_SYS_CLOCK_DIV_8 = MXC_S_GCR_CLK_CTRL_PSC_DIV8,
    MXC_SYS_CLOCK_DIV_16 = MXC_S_GCR_CLK_CTRL_PSC_DIV16,
    MXC_SYS_CLOCK_DIV_32 = MXC_S_GCR_CLK_CTRL_PSC_DIV32,
    MXC_SYS_CLOCK_DIV_64 = MXC_S_GCR_CLK_CTRL_PSC_DIV64,
    MXC_SYS_CLOCK_DIV_128 = MXC_S_GCR_CLK_CTRL_PSC_DIV128
} mxc_sys_system_clock_div_t;
 
#define MXC_SYS_USN_LEN 8
 
/***** Function Prototypes *****/
 
typedef struct {
    int ie_status;
    int in_critical;
} mxc_crit_state_t;
 
static mxc_crit_state_t _state = { .ie_status = (int)0xFFFFFFFF, .in_critical = 0 };
 
static inline void _mxc_crit_get_state(void)
{
#ifndef __riscv
    /*
        On ARM M the 0th bit of the Priority Mask register indicates
        whether interrupts are enabled or not.
 
        0 = enabled
        1 = disabled
    */
    uint32_t primask = __get_PRIMASK();
    _state.ie_status = (primask == 0);
#else
    /*
        On RISC-V bit position 3 (Machine Interrupt Enable) of the
        mstatus register indicates whether interrupts are enabled.
 
        0 = disabled
        1 = enabled
    */
    uint32_t mstatus = get_mstatus();
    _state.ie_status = ((mstatus & (1 << 3)) != 0);
#endif
}
 
static inline void MXC_SYS_Crit_Enter(void)
{
    _mxc_crit_get_state();
    if (_state.ie_status)
        __disable_irq();
    _state.in_critical = 1;
}
 
static inline void MXC_SYS_Crit_Exit(void)
{
    if (_state.ie_status) {
        __enable_irq();
    }
    _state.in_critical = 0;
    _mxc_crit_get_state();
    /*
        ^ Reset the state again to prevent edge case
        where interrupts get disabled, then Crit_Exit() gets
        called, which would inadvertently re-enable interrupts
        from old state.
    */
}
 
static inline int MXC_SYS_In_Crit_Section(void)
{
    return _state.in_critical;
}
 
// clang-format off
#define MXC_CRITICAL(code) {\
    MXC_SYS_Crit_Enter();\
    code;\
    MXC_SYS_Crit_Exit();\
}
// clang-format on
 
int MXC_SYS_GetUSN(uint8_t *usn, int len, int part);
 
int MXC_SYS_IsClockEnabled(mxc_sys_periph_clock_t clock);
 
void MXC_SYS_ClockDisable(mxc_sys_periph_clock_t clock);
 
void MXC_SYS_ClockEnable(mxc_sys_periph_clock_t clock);
 
void MXC_SYS_RTCClockEnable(void);
 
int MXC_SYS_RTCClockDisable(void);
 
int MXC_SYS_ClockSourceEnable(mxc_sys_system_clock_t clock);
 
int MXC_SYS_ClockSourceDisable(mxc_sys_system_clock_t clock);
 
int MXC_SYS_Clock_Select(mxc_sys_system_clock_t clock);
 
void MXC_SYS_SetClockDiv(mxc_sys_system_clock_div_t div);
 
mxc_sys_system_clock_div_t MXC_SYS_GetClockDiv(void);
 
int MXC_SYS_Clock_Timeout(uint32_t ready);
 
void MXC_SYS_Reset_Periph(mxc_sys_reset_t reset);
 
int MXC_SYS_LockDAP_Permanent(void);
 
#ifdef __cplusplus
}
#endif
 
#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32660_MXC_SYS_H_