DMA_INTR

Macros
#define	MXC_F_DMA_INTR_CH0_IPEND_POS   0
#define	MXC_F_DMA_INTR_CH0_IPEND   ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH0_IPEND_POS))
#define	MXC_F_DMA_INTR_CH1_IPEND_POS   1
#define	MXC_F_DMA_INTR_CH1_IPEND   ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH1_IPEND_POS))
#define	MXC_F_DMA_INTR_CH2_IPEND_POS   2
#define	MXC_F_DMA_INTR_CH2_IPEND   ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH2_IPEND_POS))
#define	MXC_F_DMA_INTR_CH3_IPEND_POS   3
#define	MXC_F_DMA_INTR_CH3_IPEND   ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH3_IPEND_POS))
#define	MXC_F_DMA_INTR_CH4_IPEND_POS   4
#define	MXC_F_DMA_INTR_CH4_IPEND   ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH4_IPEND_POS))
#define	MXC_F_DMA_INTR_CH5_IPEND_POS   5
#define	MXC_F_DMA_INTR_CH5_IPEND   ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH5_IPEND_POS))
#define	MXC_F_DMA_INTR_CH6_IPEND_POS   6
#define	MXC_F_DMA_INTR_CH6_IPEND   ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH6_IPEND_POS))
#define	MXC_F_DMA_INTR_CH7_IPEND_POS   7
#define	MXC_F_DMA_INTR_CH7_IPEND   ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH7_IPEND_POS))

Detailed Description

DMA Interrupt Register.

Macro Definition Documentation

MXC_F_DMA_INTR_CH0_IPEND

#define MXC_F_DMA_INTR_CH0_IPEND   ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH0_IPEND_POS))

INTR_CH0_IPEND Mask

MXC_F_DMA_INTR_CH0_IPEND_POS

#define MXC_F_DMA_INTR_CH0_IPEND_POS   0

INTR_CH0_IPEND Position

MXC_F_DMA_INTR_CH1_IPEND

#define MXC_F_DMA_INTR_CH1_IPEND   ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH1_IPEND_POS))

INTR_CH1_IPEND Mask

MXC_F_DMA_INTR_CH1_IPEND_POS

#define MXC_F_DMA_INTR_CH1_IPEND_POS   1

INTR_CH1_IPEND Position

MXC_F_DMA_INTR_CH2_IPEND

#define MXC_F_DMA_INTR_CH2_IPEND   ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH2_IPEND_POS))

INTR_CH2_IPEND Mask

MXC_F_DMA_INTR_CH2_IPEND_POS

#define MXC_F_DMA_INTR_CH2_IPEND_POS   2

INTR_CH2_IPEND Position

MXC_F_DMA_INTR_CH3_IPEND

#define MXC_F_DMA_INTR_CH3_IPEND   ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH3_IPEND_POS))

INTR_CH3_IPEND Mask

MXC_F_DMA_INTR_CH3_IPEND_POS

#define MXC_F_DMA_INTR_CH3_IPEND_POS   3

INTR_CH3_IPEND Position

MXC_F_DMA_INTR_CH4_IPEND

#define MXC_F_DMA_INTR_CH4_IPEND   ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH4_IPEND_POS))

INTR_CH4_IPEND Mask

MXC_F_DMA_INTR_CH4_IPEND_POS

#define MXC_F_DMA_INTR_CH4_IPEND_POS   4

INTR_CH4_IPEND Position

MXC_F_DMA_INTR_CH5_IPEND

#define MXC_F_DMA_INTR_CH5_IPEND   ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH5_IPEND_POS))

INTR_CH5_IPEND Mask

MXC_F_DMA_INTR_CH5_IPEND_POS

#define MXC_F_DMA_INTR_CH5_IPEND_POS   5

INTR_CH5_IPEND Position

MXC_F_DMA_INTR_CH6_IPEND

#define MXC_F_DMA_INTR_CH6_IPEND   ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH6_IPEND_POS))

INTR_CH6_IPEND Mask

MXC_F_DMA_INTR_CH6_IPEND_POS

#define MXC_F_DMA_INTR_CH6_IPEND_POS   6

INTR_CH6_IPEND Position

MXC_F_DMA_INTR_CH7_IPEND

#define MXC_F_DMA_INTR_CH7_IPEND   ((uint32_t)(0x1UL << MXC_F_DMA_INTR_CH7_IPEND_POS))

INTR_CH7_IPEND Mask

MXC_F_DMA_INTR_CH7_IPEND_POS

#define MXC_F_DMA_INTR_CH7_IPEND_POS   7

INTR_CH7_IPEND Position