Macros
#define	MXC_F_DMA_ST_CH_ST_POS 0

#define	MXC_F_DMA_ST_CH_ST ((uint32_t)(0x1UL << MXC_F_DMA_ST_CH_ST_POS))

#define	MXC_F_DMA_ST_IPEND_POS 1

#define	MXC_F_DMA_ST_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_ST_IPEND_POS))

#define	MXC_F_DMA_ST_CTZ_ST_POS 2

#define	MXC_F_DMA_ST_CTZ_ST ((uint32_t)(0x1UL << MXC_F_DMA_ST_CTZ_ST_POS))

#define	MXC_F_DMA_ST_RLD_ST_POS 3

#define	MXC_F_DMA_ST_RLD_ST ((uint32_t)(0x1UL << MXC_F_DMA_ST_RLD_ST_POS))

#define	MXC_F_DMA_ST_BUS_ERR_POS 4

#define	MXC_F_DMA_ST_BUS_ERR ((uint32_t)(0x1UL << MXC_F_DMA_ST_BUS_ERR_POS))

#define	MXC_F_DMA_ST_TO_ST_POS 6

#define	MXC_F_DMA_ST_TO_ST ((uint32_t)(0x1UL << MXC_F_DMA_ST_TO_ST_POS))

Detailed Description

DMA Channel Status Register.

Macro Definition Documentation

◆ MXC_F_DMA_ST_BUS_ERR

#define MXC_F_DMA_ST_BUS_ERR ((uint32_t)(0x1UL << MXC_F_DMA_ST_BUS_ERR_POS))

ST_BUS_ERR Mask

◆ MXC_F_DMA_ST_BUS_ERR_POS

#define MXC_F_DMA_ST_BUS_ERR_POS 4

ST_BUS_ERR Position

◆ MXC_F_DMA_ST_CH_ST

#define MXC_F_DMA_ST_CH_ST ((uint32_t)(0x1UL << MXC_F_DMA_ST_CH_ST_POS))

ST_CH_ST Mask

◆ MXC_F_DMA_ST_CH_ST_POS

#define MXC_F_DMA_ST_CH_ST_POS 0

ST_CH_ST Position

◆ MXC_F_DMA_ST_CTZ_ST

#define MXC_F_DMA_ST_CTZ_ST ((uint32_t)(0x1UL << MXC_F_DMA_ST_CTZ_ST_POS))

ST_CTZ_ST Mask

◆ MXC_F_DMA_ST_CTZ_ST_POS

#define MXC_F_DMA_ST_CTZ_ST_POS 2

ST_CTZ_ST Position

◆ MXC_F_DMA_ST_IPEND

#define MXC_F_DMA_ST_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_ST_IPEND_POS))

ST_IPEND Mask

◆ MXC_F_DMA_ST_IPEND_POS

#define MXC_F_DMA_ST_IPEND_POS 1

ST_IPEND Position

◆ MXC_F_DMA_ST_RLD_ST

#define MXC_F_DMA_ST_RLD_ST ((uint32_t)(0x1UL << MXC_F_DMA_ST_RLD_ST_POS))

ST_RLD_ST Mask

◆ MXC_F_DMA_ST_RLD_ST_POS

#define MXC_F_DMA_ST_RLD_ST_POS 3

ST_RLD_ST Position

◆ MXC_F_DMA_ST_TO_ST

#define MXC_F_DMA_ST_TO_ST ((uint32_t)(0x1UL << MXC_F_DMA_ST_TO_ST_POS))

ST_TO_ST Mask

◆ MXC_F_DMA_ST_TO_ST_POS

#define MXC_F_DMA_ST_TO_ST_POS 6

ST_TO_ST Position

Macros