Macros
#define	MXC_F_DVS_CTL_MON_ENA_POS 0

#define	MXC_F_DVS_CTL_MON_ENA ((uint32_t)(0x1UL << MXC_F_DVS_CTL_MON_ENA_POS))

#define	MXC_F_DVS_CTL_ADJ_ENA_POS 1

#define	MXC_F_DVS_CTL_ADJ_ENA ((uint32_t)(0x1UL << MXC_F_DVS_CTL_ADJ_ENA_POS))

#define	MXC_F_DVS_CTL_PS_FB_DIS_POS 2

#define	MXC_F_DVS_CTL_PS_FB_DIS ((uint32_t)(0x1UL << MXC_F_DVS_CTL_PS_FB_DIS_POS))

#define	MXC_F_DVS_CTL_CTRL_TAP_ENA_POS 3

#define	MXC_F_DVS_CTL_CTRL_TAP_ENA ((uint32_t)(0x1UL << MXC_F_DVS_CTL_CTRL_TAP_ENA_POS))

#define	MXC_F_DVS_CTL_PROP_DLY_POS 4

#define	MXC_F_DVS_CTL_PROP_DLY ((uint32_t)(0x3UL << MXC_F_DVS_CTL_PROP_DLY_POS))

#define	MXC_F_DVS_CTL_MON_ONESHOT_POS 6

#define	MXC_F_DVS_CTL_MON_ONESHOT ((uint32_t)(0x1UL << MXC_F_DVS_CTL_MON_ONESHOT_POS))

#define	MXC_F_DVS_CTL_GO_DIRECT_POS 7

#define	MXC_F_DVS_CTL_GO_DIRECT ((uint32_t)(0x1UL << MXC_F_DVS_CTL_GO_DIRECT_POS))

#define	MXC_F_DVS_CTL_DIRECT_REG_POS 8

#define	MXC_F_DVS_CTL_DIRECT_REG ((uint32_t)(0x1UL << MXC_F_DVS_CTL_DIRECT_REG_POS))

#define	MXC_F_DVS_CTL_PRIME_ENA_POS 9

#define	MXC_F_DVS_CTL_PRIME_ENA ((uint32_t)(0x1UL << MXC_F_DVS_CTL_PRIME_ENA_POS))

#define	MXC_F_DVS_CTL_LIMIT_IE_POS 10

#define	MXC_F_DVS_CTL_LIMIT_IE ((uint32_t)(0x1UL << MXC_F_DVS_CTL_LIMIT_IE_POS))

#define	MXC_F_DVS_CTL_RANGE_IE_POS 11

#define	MXC_F_DVS_CTL_RANGE_IE ((uint32_t)(0x1UL << MXC_F_DVS_CTL_RANGE_IE_POS))

#define	MXC_F_DVS_CTL_ADJ_IE_POS 12

#define	MXC_F_DVS_CTL_ADJ_IE ((uint32_t)(0x1UL << MXC_F_DVS_CTL_ADJ_IE_POS))

#define	MXC_F_DVS_CTL_REF_SEL_POS 13

#define	MXC_F_DVS_CTL_REF_SEL ((uint32_t)(0xFUL << MXC_F_DVS_CTL_REF_SEL_POS))

#define	MXC_F_DVS_CTL_INC_VAL_POS 17

#define	MXC_F_DVS_CTL_INC_VAL ((uint32_t)(0x7UL << MXC_F_DVS_CTL_INC_VAL_POS))

#define	MXC_F_DVS_CTL_DVS_PS_APB_DIS_POS 20

#define	MXC_F_DVS_CTL_DVS_PS_APB_DIS ((uint32_t)(0x1UL << MXC_F_DVS_CTL_DVS_PS_APB_DIS_POS))

#define	MXC_F_DVS_CTL_DVS_HI_RANGE_ANY_POS 21

#define	MXC_F_DVS_CTL_DVS_HI_RANGE_ANY ((uint32_t)(0x1UL << MXC_F_DVS_CTL_DVS_HI_RANGE_ANY_POS))

#define	MXC_F_DVS_CTL_FB_TO_IE_POS 22

#define	MXC_F_DVS_CTL_FB_TO_IE ((uint32_t)(0x1UL << MXC_F_DVS_CTL_FB_TO_IE_POS))

#define	MXC_F_DVS_CTL_FC_LV_IE_POS 23

#define	MXC_F_DVS_CTL_FC_LV_IE ((uint32_t)(0x1UL << MXC_F_DVS_CTL_FC_LV_IE_POS))

#define	MXC_F_DVS_CTL_PD_ACK_ENA_POS 24

#define	MXC_F_DVS_CTL_PD_ACK_ENA ((uint32_t)(0x1UL << MXC_F_DVS_CTL_PD_ACK_ENA_POS))

#define	MXC_F_DVS_CTL_ADJ_ABORT_POS 25

#define	MXC_F_DVS_CTL_ADJ_ABORT ((uint32_t)(0x1UL << MXC_F_DVS_CTL_ADJ_ABORT_POS))

Detailed Description

Control Register.

Macro Definition Documentation

◆ MXC_F_DVS_CTL_ADJ_ABORT

#define MXC_F_DVS_CTL_ADJ_ABORT ((uint32_t)(0x1UL << MXC_F_DVS_CTL_ADJ_ABORT_POS))

CTL_ADJ_ABORT Mask

◆ MXC_F_DVS_CTL_ADJ_ABORT_POS

#define MXC_F_DVS_CTL_ADJ_ABORT_POS 25

CTL_ADJ_ABORT Position

◆ MXC_F_DVS_CTL_ADJ_ENA

#define MXC_F_DVS_CTL_ADJ_ENA ((uint32_t)(0x1UL << MXC_F_DVS_CTL_ADJ_ENA_POS))

CTL_ADJ_ENA Mask

◆ MXC_F_DVS_CTL_ADJ_ENA_POS

#define MXC_F_DVS_CTL_ADJ_ENA_POS 1

CTL_ADJ_ENA Position

◆ MXC_F_DVS_CTL_ADJ_IE

#define MXC_F_DVS_CTL_ADJ_IE ((uint32_t)(0x1UL << MXC_F_DVS_CTL_ADJ_IE_POS))

CTL_ADJ_IE Mask

◆ MXC_F_DVS_CTL_ADJ_IE_POS

#define MXC_F_DVS_CTL_ADJ_IE_POS 12

CTL_ADJ_IE Position

◆ MXC_F_DVS_CTL_CTRL_TAP_ENA

#define MXC_F_DVS_CTL_CTRL_TAP_ENA ((uint32_t)(0x1UL << MXC_F_DVS_CTL_CTRL_TAP_ENA_POS))

CTL_CTRL_TAP_ENA Mask

◆ MXC_F_DVS_CTL_CTRL_TAP_ENA_POS

#define MXC_F_DVS_CTL_CTRL_TAP_ENA_POS 3

CTL_CTRL_TAP_ENA Position

◆ MXC_F_DVS_CTL_DIRECT_REG

#define MXC_F_DVS_CTL_DIRECT_REG ((uint32_t)(0x1UL << MXC_F_DVS_CTL_DIRECT_REG_POS))

CTL_DIRECT_REG Mask

◆ MXC_F_DVS_CTL_DIRECT_REG_POS

#define MXC_F_DVS_CTL_DIRECT_REG_POS 8

CTL_DIRECT_REG Position

◆ MXC_F_DVS_CTL_DVS_HI_RANGE_ANY

#define MXC_F_DVS_CTL_DVS_HI_RANGE_ANY ((uint32_t)(0x1UL << MXC_F_DVS_CTL_DVS_HI_RANGE_ANY_POS))

CTL_DVS_HI_RANGE_ANY Mask

◆ MXC_F_DVS_CTL_DVS_HI_RANGE_ANY_POS

#define MXC_F_DVS_CTL_DVS_HI_RANGE_ANY_POS 21

CTL_DVS_HI_RANGE_ANY Position

◆ MXC_F_DVS_CTL_DVS_PS_APB_DIS

#define MXC_F_DVS_CTL_DVS_PS_APB_DIS ((uint32_t)(0x1UL << MXC_F_DVS_CTL_DVS_PS_APB_DIS_POS))

CTL_DVS_PS_APB_DIS Mask

◆ MXC_F_DVS_CTL_DVS_PS_APB_DIS_POS

#define MXC_F_DVS_CTL_DVS_PS_APB_DIS_POS 20

CTL_DVS_PS_APB_DIS Position

◆ MXC_F_DVS_CTL_FB_TO_IE

#define MXC_F_DVS_CTL_FB_TO_IE ((uint32_t)(0x1UL << MXC_F_DVS_CTL_FB_TO_IE_POS))

CTL_FB_TO_IE Mask

◆ MXC_F_DVS_CTL_FB_TO_IE_POS

#define MXC_F_DVS_CTL_FB_TO_IE_POS 22

CTL_FB_TO_IE Position

◆ MXC_F_DVS_CTL_FC_LV_IE

#define MXC_F_DVS_CTL_FC_LV_IE ((uint32_t)(0x1UL << MXC_F_DVS_CTL_FC_LV_IE_POS))

CTL_FC_LV_IE Mask

◆ MXC_F_DVS_CTL_FC_LV_IE_POS

#define MXC_F_DVS_CTL_FC_LV_IE_POS 23

CTL_FC_LV_IE Position

◆ MXC_F_DVS_CTL_GO_DIRECT

#define MXC_F_DVS_CTL_GO_DIRECT ((uint32_t)(0x1UL << MXC_F_DVS_CTL_GO_DIRECT_POS))

CTL_GO_DIRECT Mask

◆ MXC_F_DVS_CTL_GO_DIRECT_POS

#define MXC_F_DVS_CTL_GO_DIRECT_POS 7

CTL_GO_DIRECT Position

◆ MXC_F_DVS_CTL_INC_VAL

#define MXC_F_DVS_CTL_INC_VAL ((uint32_t)(0x7UL << MXC_F_DVS_CTL_INC_VAL_POS))

CTL_INC_VAL Mask

◆ MXC_F_DVS_CTL_INC_VAL_POS

#define MXC_F_DVS_CTL_INC_VAL_POS 17

CTL_INC_VAL Position

◆ MXC_F_DVS_CTL_LIMIT_IE

#define MXC_F_DVS_CTL_LIMIT_IE ((uint32_t)(0x1UL << MXC_F_DVS_CTL_LIMIT_IE_POS))

CTL_LIMIT_IE Mask

◆ MXC_F_DVS_CTL_LIMIT_IE_POS

#define MXC_F_DVS_CTL_LIMIT_IE_POS 10

CTL_LIMIT_IE Position

◆ MXC_F_DVS_CTL_MON_ENA

#define MXC_F_DVS_CTL_MON_ENA ((uint32_t)(0x1UL << MXC_F_DVS_CTL_MON_ENA_POS))

CTL_MON_ENA Mask

◆ MXC_F_DVS_CTL_MON_ENA_POS

#define MXC_F_DVS_CTL_MON_ENA_POS 0

CTL_MON_ENA Position

◆ MXC_F_DVS_CTL_MON_ONESHOT

#define MXC_F_DVS_CTL_MON_ONESHOT ((uint32_t)(0x1UL << MXC_F_DVS_CTL_MON_ONESHOT_POS))

CTL_MON_ONESHOT Mask

◆ MXC_F_DVS_CTL_MON_ONESHOT_POS

#define MXC_F_DVS_CTL_MON_ONESHOT_POS 6

CTL_MON_ONESHOT Position

◆ MXC_F_DVS_CTL_PD_ACK_ENA

#define MXC_F_DVS_CTL_PD_ACK_ENA ((uint32_t)(0x1UL << MXC_F_DVS_CTL_PD_ACK_ENA_POS))

CTL_PD_ACK_ENA Mask

◆ MXC_F_DVS_CTL_PD_ACK_ENA_POS

#define MXC_F_DVS_CTL_PD_ACK_ENA_POS 24

CTL_PD_ACK_ENA Position

◆ MXC_F_DVS_CTL_PRIME_ENA

#define MXC_F_DVS_CTL_PRIME_ENA ((uint32_t)(0x1UL << MXC_F_DVS_CTL_PRIME_ENA_POS))

CTL_PRIME_ENA Mask

◆ MXC_F_DVS_CTL_PRIME_ENA_POS

#define MXC_F_DVS_CTL_PRIME_ENA_POS 9

CTL_PRIME_ENA Position

◆ MXC_F_DVS_CTL_PROP_DLY

#define MXC_F_DVS_CTL_PROP_DLY ((uint32_t)(0x3UL << MXC_F_DVS_CTL_PROP_DLY_POS))

CTL_PROP_DLY Mask

◆ MXC_F_DVS_CTL_PROP_DLY_POS

#define MXC_F_DVS_CTL_PROP_DLY_POS 4

CTL_PROP_DLY Position

◆ MXC_F_DVS_CTL_PS_FB_DIS

#define MXC_F_DVS_CTL_PS_FB_DIS ((uint32_t)(0x1UL << MXC_F_DVS_CTL_PS_FB_DIS_POS))

CTL_PS_FB_DIS Mask

◆ MXC_F_DVS_CTL_PS_FB_DIS_POS

#define MXC_F_DVS_CTL_PS_FB_DIS_POS 2

CTL_PS_FB_DIS Position

◆ MXC_F_DVS_CTL_RANGE_IE

#define MXC_F_DVS_CTL_RANGE_IE ((uint32_t)(0x1UL << MXC_F_DVS_CTL_RANGE_IE_POS))

CTL_RANGE_IE Mask

◆ MXC_F_DVS_CTL_RANGE_IE_POS

#define MXC_F_DVS_CTL_RANGE_IE_POS 11

CTL_RANGE_IE Position

◆ MXC_F_DVS_CTL_REF_SEL

#define MXC_F_DVS_CTL_REF_SEL ((uint32_t)(0xFUL << MXC_F_DVS_CTL_REF_SEL_POS))

CTL_REF_SEL Mask

◆ MXC_F_DVS_CTL_REF_SEL_POS

#define MXC_F_DVS_CTL_REF_SEL_POS 13

CTL_REF_SEL Position

Macros