GCR_ECC_ER

Macros
#define	MXC_F_GCR_ECC_ER_SYSRAM0ECCERR_POS   0
#define	MXC_F_GCR_ECC_ER_SYSRAM0ECCERR   ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_SYSRAM0ECCERR_POS))
#define	MXC_F_GCR_ECC_ER_SYSRAM1ECCERR_POS   1
#define	MXC_F_GCR_ECC_ER_SYSRAM1ECCERR   ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_SYSRAM1ECCERR_POS))
#define	MXC_F_GCR_ECC_ER_SYSRAM2ECCERR_POS   2
#define	MXC_F_GCR_ECC_ER_SYSRAM2ECCERR   ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_SYSRAM2ECCERR_POS))
#define	MXC_F_GCR_ECC_ER_SYSRAM3ECCERR_POS   3
#define	MXC_F_GCR_ECC_ER_SYSRAM3ECCERR   ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_SYSRAM3ECCERR_POS))
#define	MXC_F_GCR_ECC_ER_SYSRAM4ECCERR_POS   4
#define	MXC_F_GCR_ECC_ER_SYSRAM4ECCERR   ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_SYSRAM4ECCERR_POS))
#define	MXC_F_GCR_ECC_ER_SYSRAM5ECCERR_POS   5
#define	MXC_F_GCR_ECC_ER_SYSRAM5ECCERR   ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_SYSRAM5ECCERR_POS))
#define	MXC_F_GCR_ECC_ER_SYSRAM6ECCERR_POS   6
#define	MXC_F_GCR_ECC_ER_SYSRAM6ECCERR   ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_SYSRAM6ECCERR_POS))
#define	MXC_F_GCR_ECC_ER_IC0ECCERR_POS   8
#define	MXC_F_GCR_ECC_ER_IC0ECCERR   ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_IC0ECCERR_POS))
#define	MXC_F_GCR_ECC_ER_IC1ECCERR_POS   9
#define	MXC_F_GCR_ECC_ER_IC1ECCERR   ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_IC1ECCERR_POS))
#define	MXC_F_GCR_ECC_ER_ICXIPECCERR_POS   10
#define	MXC_F_GCR_ECC_ER_ICXIPECCERR   ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_ICXIPECCERR_POS))
#define	MXC_F_GCR_ECC_ER_FL0ECCERR_POS   11
#define	MXC_F_GCR_ECC_ER_FL0ECCERR   ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_FL0ECCERR_POS))
#define	MXC_F_GCR_ECC_ER_FL1ECCERR_POS   12
#define	MXC_F_GCR_ECC_ER_FL1ECCERR   ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_FL1ECCERR_POS))

Detailed Description

ECC Error Register.

Macro Definition Documentation

MXC_F_GCR_ECC_ER_FL0ECCERR

#define MXC_F_GCR_ECC_ER_FL0ECCERR   ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_FL0ECCERR_POS))

ECC_ER_FL0ECCERR Mask

MXC_F_GCR_ECC_ER_FL0ECCERR_POS

#define MXC_F_GCR_ECC_ER_FL0ECCERR_POS   11

ECC_ER_FL0ECCERR Position

MXC_F_GCR_ECC_ER_FL1ECCERR

#define MXC_F_GCR_ECC_ER_FL1ECCERR   ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_FL1ECCERR_POS))

ECC_ER_FL1ECCERR Mask

MXC_F_GCR_ECC_ER_FL1ECCERR_POS

#define MXC_F_GCR_ECC_ER_FL1ECCERR_POS   12

ECC_ER_FL1ECCERR Position

MXC_F_GCR_ECC_ER_IC0ECCERR

#define MXC_F_GCR_ECC_ER_IC0ECCERR   ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_IC0ECCERR_POS))

ECC_ER_IC0ECCERR Mask

MXC_F_GCR_ECC_ER_IC0ECCERR_POS

#define MXC_F_GCR_ECC_ER_IC0ECCERR_POS   8

ECC_ER_IC0ECCERR Position

MXC_F_GCR_ECC_ER_IC1ECCERR

#define MXC_F_GCR_ECC_ER_IC1ECCERR   ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_IC1ECCERR_POS))

ECC_ER_IC1ECCERR Mask

MXC_F_GCR_ECC_ER_IC1ECCERR_POS

#define MXC_F_GCR_ECC_ER_IC1ECCERR_POS   9

ECC_ER_IC1ECCERR Position

MXC_F_GCR_ECC_ER_ICXIPECCERR

#define MXC_F_GCR_ECC_ER_ICXIPECCERR   ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_ICXIPECCERR_POS))

ECC_ER_ICXIPECCERR Mask

MXC_F_GCR_ECC_ER_ICXIPECCERR_POS

#define MXC_F_GCR_ECC_ER_ICXIPECCERR_POS   10

ECC_ER_ICXIPECCERR Position

MXC_F_GCR_ECC_ER_SYSRAM0ECCERR

#define MXC_F_GCR_ECC_ER_SYSRAM0ECCERR   ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_SYSRAM0ECCERR_POS))

ECC_ER_SYSRAM0ECCERR Mask

MXC_F_GCR_ECC_ER_SYSRAM0ECCERR_POS

#define MXC_F_GCR_ECC_ER_SYSRAM0ECCERR_POS   0

ECC_ER_SYSRAM0ECCERR Position

MXC_F_GCR_ECC_ER_SYSRAM1ECCERR

#define MXC_F_GCR_ECC_ER_SYSRAM1ECCERR   ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_SYSRAM1ECCERR_POS))

ECC_ER_SYSRAM1ECCERR Mask

MXC_F_GCR_ECC_ER_SYSRAM1ECCERR_POS

#define MXC_F_GCR_ECC_ER_SYSRAM1ECCERR_POS   1

ECC_ER_SYSRAM1ECCERR Position

MXC_F_GCR_ECC_ER_SYSRAM2ECCERR

#define MXC_F_GCR_ECC_ER_SYSRAM2ECCERR   ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_SYSRAM2ECCERR_POS))

ECC_ER_SYSRAM2ECCERR Mask

MXC_F_GCR_ECC_ER_SYSRAM2ECCERR_POS

#define MXC_F_GCR_ECC_ER_SYSRAM2ECCERR_POS   2

ECC_ER_SYSRAM2ECCERR Position

MXC_F_GCR_ECC_ER_SYSRAM3ECCERR

#define MXC_F_GCR_ECC_ER_SYSRAM3ECCERR   ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_SYSRAM3ECCERR_POS))

ECC_ER_SYSRAM3ECCERR Mask

MXC_F_GCR_ECC_ER_SYSRAM3ECCERR_POS

#define MXC_F_GCR_ECC_ER_SYSRAM3ECCERR_POS   3

ECC_ER_SYSRAM3ECCERR Position

MXC_F_GCR_ECC_ER_SYSRAM4ECCERR

#define MXC_F_GCR_ECC_ER_SYSRAM4ECCERR   ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_SYSRAM4ECCERR_POS))

ECC_ER_SYSRAM4ECCERR Mask

MXC_F_GCR_ECC_ER_SYSRAM4ECCERR_POS

#define MXC_F_GCR_ECC_ER_SYSRAM4ECCERR_POS   4

ECC_ER_SYSRAM4ECCERR Position

MXC_F_GCR_ECC_ER_SYSRAM5ECCERR

#define MXC_F_GCR_ECC_ER_SYSRAM5ECCERR   ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_SYSRAM5ECCERR_POS))

ECC_ER_SYSRAM5ECCERR Mask

MXC_F_GCR_ECC_ER_SYSRAM5ECCERR_POS

#define MXC_F_GCR_ECC_ER_SYSRAM5ECCERR_POS   5

ECC_ER_SYSRAM5ECCERR Position

MXC_F_GCR_ECC_ER_SYSRAM6ECCERR

#define MXC_F_GCR_ECC_ER_SYSRAM6ECCERR   ((uint32_t)(0x1UL << MXC_F_GCR_ECC_ER_SYSRAM6ECCERR_POS))

ECC_ER_SYSRAM6ECCERR Mask

MXC_F_GCR_ECC_ER_SYSRAM6ECCERR_POS

#define MXC_F_GCR_ECC_ER_SYSRAM6ECCERR_POS   6

ECC_ER_SYSRAM6ECCERR Position