GCR_RSTR0

Macros
#define	MXC_F_GCR_RSTR0_DMA_POS   0
#define	MXC_F_GCR_RSTR0_DMA   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_DMA_POS))
#define	MXC_F_GCR_RSTR0_WDT0_POS   1
#define	MXC_F_GCR_RSTR0_WDT0   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_WDT0_POS))
#define	MXC_F_GCR_RSTR0_GPIO0_POS   2
#define	MXC_F_GCR_RSTR0_GPIO0   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_GPIO0_POS))
#define	MXC_F_GCR_RSTR0_GPIO1_POS   3
#define	MXC_F_GCR_RSTR0_GPIO1   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_GPIO1_POS))
#define	MXC_F_GCR_RSTR0_TIMER0_POS   5
#define	MXC_F_GCR_RSTR0_TIMER0   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER0_POS))
#define	MXC_F_GCR_RSTR0_TIMER1_POS   6
#define	MXC_F_GCR_RSTR0_TIMER1   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER1_POS))
#define	MXC_F_GCR_RSTR0_TIMER2_POS   7
#define	MXC_F_GCR_RSTR0_TIMER2   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER2_POS))
#define	MXC_F_GCR_RSTR0_TIMER3_POS   8
#define	MXC_F_GCR_RSTR0_TIMER3   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER3_POS))
#define	MXC_F_GCR_RSTR0_TIMER4_POS   9
#define	MXC_F_GCR_RSTR0_TIMER4   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER4_POS))
#define	MXC_F_GCR_RSTR0_TIMER5_POS   10
#define	MXC_F_GCR_RSTR0_TIMER5   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER5_POS))
#define	MXC_F_GCR_RSTR0_UART0_POS   11
#define	MXC_F_GCR_RSTR0_UART0   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_UART0_POS))
#define	MXC_F_GCR_RSTR0_UART1_POS   12
#define	MXC_F_GCR_RSTR0_UART1   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_UART1_POS))
#define	MXC_F_GCR_RSTR0_SPI1_POS   13
#define	MXC_F_GCR_RSTR0_SPI1   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI1_POS))
#define	MXC_F_GCR_RSTR0_SPI2_POS   14
#define	MXC_F_GCR_RSTR0_SPI2   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI2_POS))
#define	MXC_F_GCR_RSTR0_I2C0_POS   16
#define	MXC_F_GCR_RSTR0_I2C0   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_I2C0_POS))
#define	MXC_F_GCR_RSTR0_RTC_POS   17
#define	MXC_F_GCR_RSTR0_RTC   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_RTC_POS))
#define	MXC_F_GCR_RSTR0_CRYPTO_POS   18
#define	MXC_F_GCR_RSTR0_CRYPTO   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_CRYPTO_POS))
#define	MXC_F_GCR_RSTR0_SMPHR_POS   22
#define	MXC_F_GCR_RSTR0_SMPHR   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SMPHR_POS))
#define	MXC_F_GCR_RSTR0_USB_POS   23
#define	MXC_F_GCR_RSTR0_USB   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_USB_POS))
#define	MXC_F_GCR_RSTR0_ADC_POS   26
#define	MXC_F_GCR_RSTR0_ADC   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_ADC_POS))
#define	MXC_F_GCR_RSTR0_DMA1_POS   27
#define	MXC_F_GCR_RSTR0_DMA1   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_DMA1_POS))
#define	MXC_F_GCR_RSTR0_UART2_POS   28
#define	MXC_F_GCR_RSTR0_UART2   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_UART2_POS))
#define	MXC_F_GCR_RSTR0_SRST_POS   29
#define	MXC_F_GCR_RSTR0_SRST   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SRST_POS))
#define	MXC_F_GCR_RSTR0_PRST_POS   30
#define	MXC_F_GCR_RSTR0_PRST   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_PRST_POS))
#define	MXC_F_GCR_RSTR0_SYSTEM_POS   31
#define	MXC_F_GCR_RSTR0_SYSTEM   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SYSTEM_POS))

Detailed Description

Reset.

Macro Definition Documentation

MXC_F_GCR_RSTR0_ADC

#define MXC_F_GCR_RSTR0_ADC   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_ADC_POS))

RSTR0_ADC Mask

MXC_F_GCR_RSTR0_ADC_POS

#define MXC_F_GCR_RSTR0_ADC_POS   26

RSTR0_ADC Position

MXC_F_GCR_RSTR0_CRYPTO

#define MXC_F_GCR_RSTR0_CRYPTO   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_CRYPTO_POS))

RSTR0_CRYPTO Mask

MXC_F_GCR_RSTR0_CRYPTO_POS

#define MXC_F_GCR_RSTR0_CRYPTO_POS   18

RSTR0_CRYPTO Position

MXC_F_GCR_RSTR0_DMA

#define MXC_F_GCR_RSTR0_DMA   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_DMA_POS))

RSTR0_DMA Mask

MXC_F_GCR_RSTR0_DMA1

#define MXC_F_GCR_RSTR0_DMA1   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_DMA1_POS))

RSTR0_DMA1 Mask

MXC_F_GCR_RSTR0_DMA1_POS

#define MXC_F_GCR_RSTR0_DMA1_POS   27

RSTR0_DMA1 Position

MXC_F_GCR_RSTR0_DMA_POS

#define MXC_F_GCR_RSTR0_DMA_POS   0

RSTR0_DMA Position

MXC_F_GCR_RSTR0_GPIO0

#define MXC_F_GCR_RSTR0_GPIO0   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_GPIO0_POS))

RSTR0_GPIO0 Mask

MXC_F_GCR_RSTR0_GPIO0_POS

#define MXC_F_GCR_RSTR0_GPIO0_POS   2

RSTR0_GPIO0 Position

MXC_F_GCR_RSTR0_GPIO1

#define MXC_F_GCR_RSTR0_GPIO1   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_GPIO1_POS))

RSTR0_GPIO1 Mask

MXC_F_GCR_RSTR0_GPIO1_POS

#define MXC_F_GCR_RSTR0_GPIO1_POS   3

RSTR0_GPIO1 Position

MXC_F_GCR_RSTR0_I2C0

#define MXC_F_GCR_RSTR0_I2C0   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_I2C0_POS))

RSTR0_I2C0 Mask

MXC_F_GCR_RSTR0_I2C0_POS

#define MXC_F_GCR_RSTR0_I2C0_POS   16

RSTR0_I2C0 Position

MXC_F_GCR_RSTR0_PRST

#define MXC_F_GCR_RSTR0_PRST   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_PRST_POS))

RSTR0_PRST Mask

MXC_F_GCR_RSTR0_PRST_POS

#define MXC_F_GCR_RSTR0_PRST_POS   30

RSTR0_PRST Position

MXC_F_GCR_RSTR0_RTC

#define MXC_F_GCR_RSTR0_RTC   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_RTC_POS))

RSTR0_RTC Mask

MXC_F_GCR_RSTR0_RTC_POS

#define MXC_F_GCR_RSTR0_RTC_POS   17

RSTR0_RTC Position

MXC_F_GCR_RSTR0_SMPHR

#define MXC_F_GCR_RSTR0_SMPHR   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SMPHR_POS))

RSTR0_SMPHR Mask

MXC_F_GCR_RSTR0_SMPHR_POS

#define MXC_F_GCR_RSTR0_SMPHR_POS   22

RSTR0_SMPHR Position

MXC_F_GCR_RSTR0_SPI1

#define MXC_F_GCR_RSTR0_SPI1   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI1_POS))

RSTR0_SPI1 Mask

MXC_F_GCR_RSTR0_SPI1_POS

#define MXC_F_GCR_RSTR0_SPI1_POS   13

RSTR0_SPI1 Position

MXC_F_GCR_RSTR0_SPI2

#define MXC_F_GCR_RSTR0_SPI2   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI2_POS))

RSTR0_SPI2 Mask

MXC_F_GCR_RSTR0_SPI2_POS

#define MXC_F_GCR_RSTR0_SPI2_POS   14

RSTR0_SPI2 Position

MXC_F_GCR_RSTR0_SRST

#define MXC_F_GCR_RSTR0_SRST   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SRST_POS))

RSTR0_SRST Mask

MXC_F_GCR_RSTR0_SRST_POS

#define MXC_F_GCR_RSTR0_SRST_POS   29

RSTR0_SRST Position

MXC_F_GCR_RSTR0_SYSTEM

#define MXC_F_GCR_RSTR0_SYSTEM   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SYSTEM_POS))

RSTR0_SYSTEM Mask

MXC_F_GCR_RSTR0_SYSTEM_POS

#define MXC_F_GCR_RSTR0_SYSTEM_POS   31

RSTR0_SYSTEM Position

MXC_F_GCR_RSTR0_TIMER0

#define MXC_F_GCR_RSTR0_TIMER0   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER0_POS))

RSTR0_TIMER0 Mask

MXC_F_GCR_RSTR0_TIMER0_POS

#define MXC_F_GCR_RSTR0_TIMER0_POS   5

RSTR0_TIMER0 Position

MXC_F_GCR_RSTR0_TIMER1

#define MXC_F_GCR_RSTR0_TIMER1   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER1_POS))

RSTR0_TIMER1 Mask

MXC_F_GCR_RSTR0_TIMER1_POS

#define MXC_F_GCR_RSTR0_TIMER1_POS   6

RSTR0_TIMER1 Position

MXC_F_GCR_RSTR0_TIMER2

#define MXC_F_GCR_RSTR0_TIMER2   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER2_POS))

RSTR0_TIMER2 Mask

MXC_F_GCR_RSTR0_TIMER2_POS

#define MXC_F_GCR_RSTR0_TIMER2_POS   7

RSTR0_TIMER2 Position

MXC_F_GCR_RSTR0_TIMER3

#define MXC_F_GCR_RSTR0_TIMER3   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER3_POS))

RSTR0_TIMER3 Mask

MXC_F_GCR_RSTR0_TIMER3_POS

#define MXC_F_GCR_RSTR0_TIMER3_POS   8

RSTR0_TIMER3 Position

MXC_F_GCR_RSTR0_TIMER4

#define MXC_F_GCR_RSTR0_TIMER4   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER4_POS))

RSTR0_TIMER4 Mask

MXC_F_GCR_RSTR0_TIMER4_POS

#define MXC_F_GCR_RSTR0_TIMER4_POS   9

RSTR0_TIMER4 Position

MXC_F_GCR_RSTR0_TIMER5

#define MXC_F_GCR_RSTR0_TIMER5   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER5_POS))

RSTR0_TIMER5 Mask

MXC_F_GCR_RSTR0_TIMER5_POS

#define MXC_F_GCR_RSTR0_TIMER5_POS   10

RSTR0_TIMER5 Position

MXC_F_GCR_RSTR0_UART0

#define MXC_F_GCR_RSTR0_UART0   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_UART0_POS))

RSTR0_UART0 Mask

MXC_F_GCR_RSTR0_UART0_POS

#define MXC_F_GCR_RSTR0_UART0_POS   11

RSTR0_UART0 Position

MXC_F_GCR_RSTR0_UART1

#define MXC_F_GCR_RSTR0_UART1   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_UART1_POS))

RSTR0_UART1 Mask

MXC_F_GCR_RSTR0_UART1_POS

#define MXC_F_GCR_RSTR0_UART1_POS   12

RSTR0_UART1 Position

MXC_F_GCR_RSTR0_UART2

#define MXC_F_GCR_RSTR0_UART2   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_UART2_POS))

RSTR0_UART2 Mask

MXC_F_GCR_RSTR0_UART2_POS

#define MXC_F_GCR_RSTR0_UART2_POS   28

RSTR0_UART2 Position

MXC_F_GCR_RSTR0_USB

#define MXC_F_GCR_RSTR0_USB   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_USB_POS))

RSTR0_USB Mask

MXC_F_GCR_RSTR0_USB_POS

#define MXC_F_GCR_RSTR0_USB_POS   23

RSTR0_USB Position

MXC_F_GCR_RSTR0_WDT0

#define MXC_F_GCR_RSTR0_WDT0   ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_WDT0_POS))

RSTR0_WDT0 Mask

MXC_F_GCR_RSTR0_WDT0_POS

#define MXC_F_GCR_RSTR0_WDT0_POS   1

RSTR0_WDT0 Position