I2C_INT_FL1

Macros
#define	MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS   0
#define	MXC_F_I2C_INT_FL1_RX_OVERFLOW   ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS))
#define	MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS   1
#define	MXC_F_I2C_INT_FL1_TX_UNDERFLOW   ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS))
#define	MXC_F_I2C_INT_FL1_START_POS   2
#define	MXC_F_I2C_INT_FL1_START   ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_START_POS))

Detailed Description

Interrupt Status Register 1.

Macro Definition Documentation

MXC_F_I2C_INT_FL1_RX_OVERFLOW

#define MXC_F_I2C_INT_FL1_RX_OVERFLOW   ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS))

INT_FL1_RX_OVERFLOW Mask

MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS

#define MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS   0

INT_FL1_RX_OVERFLOW Position

MXC_F_I2C_INT_FL1_START

#define MXC_F_I2C_INT_FL1_START   ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_START_POS))

INT_FL1_START Mask

MXC_F_I2C_INT_FL1_START_POS

#define MXC_F_I2C_INT_FL1_START_POS   2

INT_FL1_START Position

MXC_F_I2C_INT_FL1_TX_UNDERFLOW

#define MXC_F_I2C_INT_FL1_TX_UNDERFLOW   ((uint32_t)(0x1UL << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS))

INT_FL1_TX_UNDERFLOW Mask

MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS

#define MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS   1

INT_FL1_TX_UNDERFLOW Position