I2C_TX_CTRL0

Macros
#define	MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS   0
#define	MXC_F_I2C_TX_CTRL0_TX_PRELOAD   ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS))
#define	MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS   1
#define	MXC_F_I2C_TX_CTRL0_TX_READY_MODE   ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS))
#define	MXC_F_I2C_TX_CTRL0_TX_AMGC_AFD_POS   2
#define	MXC_F_I2C_TX_CTRL0_TX_AMGC_AFD   ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_AMGC_AFD_POS))
#define	MXC_F_I2C_TX_CTRL0_TX_AMW_AFD_POS   3
#define	MXC_F_I2C_TX_CTRL0_TX_AMW_AFD   ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_AMW_AFD_POS))
#define	MXC_F_I2C_TX_CTRL0_TX_AMR_AFD_POS   4
#define	MXC_F_I2C_TX_CTRL0_TX_AMR_AFD   ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_AMR_AFD_POS))
#define	MXC_F_I2C_TX_CTRL0_TX_NACK_AFD_POS   5
#define	MXC_F_I2C_TX_CTRL0_TX_NACK_AFD   ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_NACK_AFD_POS))
#define	MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS   7
#define	MXC_F_I2C_TX_CTRL0_TX_FLUSH   ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS))
#define	MXC_F_I2C_TX_CTRL0_TX_THRESH_POS   8
#define	MXC_F_I2C_TX_CTRL0_TX_THRESH   ((uint32_t)(0xFUL << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS))

Detailed Description

Transmit Control Register 0.

Macro Definition Documentation

MXC_F_I2C_TX_CTRL0_TX_AMGC_AFD

#define MXC_F_I2C_TX_CTRL0_TX_AMGC_AFD   ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_AMGC_AFD_POS))

TX_CTRL0_TX_AMGC_AFD Mask

MXC_F_I2C_TX_CTRL0_TX_AMGC_AFD_POS

#define MXC_F_I2C_TX_CTRL0_TX_AMGC_AFD_POS   2

TX_CTRL0_TX_AMGC_AFD Position

MXC_F_I2C_TX_CTRL0_TX_AMR_AFD

#define MXC_F_I2C_TX_CTRL0_TX_AMR_AFD   ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_AMR_AFD_POS))

TX_CTRL0_TX_AMR_AFD Mask

MXC_F_I2C_TX_CTRL0_TX_AMR_AFD_POS

#define MXC_F_I2C_TX_CTRL0_TX_AMR_AFD_POS   4

TX_CTRL0_TX_AMR_AFD Position

MXC_F_I2C_TX_CTRL0_TX_AMW_AFD

#define MXC_F_I2C_TX_CTRL0_TX_AMW_AFD   ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_AMW_AFD_POS))

TX_CTRL0_TX_AMW_AFD Mask

MXC_F_I2C_TX_CTRL0_TX_AMW_AFD_POS

#define MXC_F_I2C_TX_CTRL0_TX_AMW_AFD_POS   3

TX_CTRL0_TX_AMW_AFD Position

MXC_F_I2C_TX_CTRL0_TX_FLUSH

#define MXC_F_I2C_TX_CTRL0_TX_FLUSH   ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS))

TX_CTRL0_TX_FLUSH Mask

MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS

#define MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS   7

TX_CTRL0_TX_FLUSH Position

MXC_F_I2C_TX_CTRL0_TX_NACK_AFD

#define MXC_F_I2C_TX_CTRL0_TX_NACK_AFD   ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_NACK_AFD_POS))

TX_CTRL0_TX_NACK_AFD Mask

MXC_F_I2C_TX_CTRL0_TX_NACK_AFD_POS

#define MXC_F_I2C_TX_CTRL0_TX_NACK_AFD_POS   5

TX_CTRL0_TX_NACK_AFD Position

MXC_F_I2C_TX_CTRL0_TX_PRELOAD

#define MXC_F_I2C_TX_CTRL0_TX_PRELOAD   ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS))

TX_CTRL0_TX_PRELOAD Mask

MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS

#define MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS   0

TX_CTRL0_TX_PRELOAD Position

MXC_F_I2C_TX_CTRL0_TX_READY_MODE

#define MXC_F_I2C_TX_CTRL0_TX_READY_MODE   ((uint32_t)(0x1UL << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS))

TX_CTRL0_TX_READY_MODE Mask

MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS

#define MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS   1

TX_CTRL0_TX_READY_MODE Position

MXC_F_I2C_TX_CTRL0_TX_THRESH

#define MXC_F_I2C_TX_CTRL0_TX_THRESH   ((uint32_t)(0xFUL << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS))

TX_CTRL0_TX_THRESH Mask

MXC_F_I2C_TX_CTRL0_TX_THRESH_POS

#define MXC_F_I2C_TX_CTRL0_TX_THRESH_POS   8

TX_CTRL0_TX_THRESH Position