MCR_HIRC96M

Macros
#define	MXC_F_MCR_HIRC96M_HIRC96MTR_POS   0
#define	MXC_F_MCR_HIRC96M_HIRC96MTR   ((uint32_t)(0x1FFUL << MXC_F_MCR_HIRC96M_HIRC96MTR_POS))
#define	MXC_V_MCR_HIRC96M_HIRC96MTR_DEFAULT   ((uint32_t)0x100UL)
#define	MXC_S_MCR_HIRC96M_HIRC96MTR_DEFAULT   (MXC_V_MCR_HIRC96M_HIRC96MTR_DEFAULT << MXC_F_MCR_HIRC96M_HIRC96MTR_POS)

Detailed Description

96MHz High Frequency Clock Adjustment Register

Macro Definition Documentation

MXC_F_MCR_HIRC96M_HIRC96MTR

#define MXC_F_MCR_HIRC96M_HIRC96MTR   ((uint32_t)(0x1FFUL << MXC_F_MCR_HIRC96M_HIRC96MTR_POS))

HIRC96M_HIRC96MTR Mask

MXC_F_MCR_HIRC96M_HIRC96MTR_POS

#define MXC_F_MCR_HIRC96M_HIRC96MTR_POS   0

HIRC96M_HIRC96MTR Position

MXC_S_MCR_HIRC96M_HIRC96MTR_DEFAULT

#define MXC_S_MCR_HIRC96M_HIRC96MTR_DEFAULT   (MXC_V_MCR_HIRC96M_HIRC96MTR_DEFAULT << MXC_F_MCR_HIRC96M_HIRC96MTR_POS)

HIRC96M_HIRC96MTR_DEFAULT Setting

MXC_V_MCR_HIRC96M_HIRC96MTR_DEFAULT

#define MXC_V_MCR_HIRC96M_HIRC96MTR_DEFAULT   ((uint32_t)0x100UL)

HIRC96M_HIRC96MTR_DEFAULT Value