SDHC_CFG_1

Macros
#define	MXC_F_SDHC_CFG_1_SDR50_POS   0
#define	MXC_F_SDHC_CFG_1_SDR50   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_SDR50_POS))
#define	MXC_F_SDHC_CFG_1_SDR104_POS   1
#define	MXC_F_SDHC_CFG_1_SDR104   ((uint32_t)(0x0UL << MXC_F_SDHC_CFG_1_SDR104_POS))
#define	MXC_F_SDHC_CFG_1_DDR50_POS   2
#define	MXC_F_SDHC_CFG_1_DDR50   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_DDR50_POS))
#define	MXC_F_SDHC_CFG_1_DRIVER_A_POS   4
#define	MXC_F_SDHC_CFG_1_DRIVER_A   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_DRIVER_A_POS))
#define	MXC_F_SDHC_CFG_1_DRIVER_C_POS   5
#define	MXC_F_SDHC_CFG_1_DRIVER_C   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_DRIVER_C_POS))
#define	MXC_F_SDHC_CFG_1_DRIVER_D_POS   6
#define	MXC_F_SDHC_CFG_1_DRIVER_D   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_DRIVER_D_POS))
#define	MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS   8
#define	MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING   ((uint32_t)(0xFUL << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS))
#define	MXC_F_SDHC_CFG_1_TUNING_SDR50_POS   13
#define	MXC_F_SDHC_CFG_1_TUNING_SDR50   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_TUNING_SDR50_POS))
#define	MXC_F_SDHC_CFG_1_RETUNING_POS   14
#define	MXC_F_SDHC_CFG_1_RETUNING   ((uint32_t)(0x3UL << MXC_F_SDHC_CFG_1_RETUNING_POS))
#define	MXC_F_SDHC_CFG_1_CLK_MULTI_POS   16
#define	MXC_F_SDHC_CFG_1_CLK_MULTI   ((uint32_t)(0xFFUL << MXC_F_SDHC_CFG_1_CLK_MULTI_POS))

Detailed Description

Capabilities 32-63.

Macro Definition Documentation

MXC_F_SDHC_CFG_1_CLK_MULTI

#define MXC_F_SDHC_CFG_1_CLK_MULTI   ((uint32_t)(0xFFUL << MXC_F_SDHC_CFG_1_CLK_MULTI_POS))

CFG_1_CLK_MULTI Mask

MXC_F_SDHC_CFG_1_CLK_MULTI_POS

#define MXC_F_SDHC_CFG_1_CLK_MULTI_POS   16

CFG_1_CLK_MULTI Position

MXC_F_SDHC_CFG_1_DDR50

#define MXC_F_SDHC_CFG_1_DDR50   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_DDR50_POS))

CFG_1_DDR50 Mask

MXC_F_SDHC_CFG_1_DDR50_POS

#define MXC_F_SDHC_CFG_1_DDR50_POS   2

CFG_1_DDR50 Position

MXC_F_SDHC_CFG_1_DRIVER_A

#define MXC_F_SDHC_CFG_1_DRIVER_A   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_DRIVER_A_POS))

CFG_1_DRIVER_A Mask

MXC_F_SDHC_CFG_1_DRIVER_A_POS

#define MXC_F_SDHC_CFG_1_DRIVER_A_POS   4

CFG_1_DRIVER_A Position

MXC_F_SDHC_CFG_1_DRIVER_C

#define MXC_F_SDHC_CFG_1_DRIVER_C   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_DRIVER_C_POS))

CFG_1_DRIVER_C Mask

MXC_F_SDHC_CFG_1_DRIVER_C_POS

#define MXC_F_SDHC_CFG_1_DRIVER_C_POS   5

CFG_1_DRIVER_C Position

MXC_F_SDHC_CFG_1_DRIVER_D

#define MXC_F_SDHC_CFG_1_DRIVER_D   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_DRIVER_D_POS))

CFG_1_DRIVER_D Mask

MXC_F_SDHC_CFG_1_DRIVER_D_POS

#define MXC_F_SDHC_CFG_1_DRIVER_D_POS   6

CFG_1_DRIVER_D Position

MXC_F_SDHC_CFG_1_RETUNING

#define MXC_F_SDHC_CFG_1_RETUNING   ((uint32_t)(0x3UL << MXC_F_SDHC_CFG_1_RETUNING_POS))

CFG_1_RETUNING Mask

MXC_F_SDHC_CFG_1_RETUNING_POS

#define MXC_F_SDHC_CFG_1_RETUNING_POS   14

CFG_1_RETUNING Position

MXC_F_SDHC_CFG_1_SDR104

#define MXC_F_SDHC_CFG_1_SDR104   ((uint32_t)(0x0UL << MXC_F_SDHC_CFG_1_SDR104_POS))

CFG_1_SDR104 Mask

MXC_F_SDHC_CFG_1_SDR104_POS

#define MXC_F_SDHC_CFG_1_SDR104_POS   1

CFG_1_SDR104 Position

MXC_F_SDHC_CFG_1_SDR50

#define MXC_F_SDHC_CFG_1_SDR50   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_SDR50_POS))

CFG_1_SDR50 Mask

MXC_F_SDHC_CFG_1_SDR50_POS

#define MXC_F_SDHC_CFG_1_SDR50_POS   0

CFG_1_SDR50 Position

MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING

#define MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING   ((uint32_t)(0xFUL << MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS))

CFG_1_TIMER_CNT_TUNING Mask

MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS

#define MXC_F_SDHC_CFG_1_TIMER_CNT_TUNING_POS   8

CFG_1_TIMER_CNT_TUNING Position

MXC_F_SDHC_CFG_1_TUNING_SDR50

#define MXC_F_SDHC_CFG_1_TUNING_SDR50   ((uint32_t)(0x1UL << MXC_F_SDHC_CFG_1_TUNING_SDR50_POS))

CFG_1_TUNING_SDR50 Mask

MXC_F_SDHC_CFG_1_TUNING_SDR50_POS

#define MXC_F_SDHC_CFG_1_TUNING_SDR50_POS   13

CFG_1_TUNING_SDR50 Position