Macros
#define	MXC_F_SPI_INT_FL_TX_THRESH_POS 0

#define	MXC_F_SPI_INT_FL_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_THRESH_POS))

#define	MXC_F_SPI_INT_FL_TX_EMPTY_POS 1

#define	MXC_F_SPI_INT_FL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_EMPTY_POS))

#define	MXC_F_SPI_INT_FL_RX_THRESH_POS 2

#define	MXC_F_SPI_INT_FL_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_THRESH_POS))

#define	MXC_F_SPI_INT_FL_RX_FULL_POS 3

#define	MXC_F_SPI_INT_FL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_FULL_POS))

#define	MXC_F_SPI_INT_FL_SSA_POS 4

#define	MXC_F_SPI_INT_FL_SSA ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_SSA_POS))

#define	MXC_F_SPI_INT_FL_SSD_POS 5

#define	MXC_F_SPI_INT_FL_SSD ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_SSD_POS))

#define	MXC_F_SPI_INT_FL_FAULT_POS 8

#define	MXC_F_SPI_INT_FL_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_FAULT_POS))

#define	MXC_F_SPI_INT_FL_ABORT_POS 9

#define	MXC_F_SPI_INT_FL_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_ABORT_POS))

#define	MXC_F_SPI_INT_FL_M_DONE_POS 11

#define	MXC_F_SPI_INT_FL_M_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_M_DONE_POS))

#define	MXC_F_SPI_INT_FL_TX_OVR_POS 12

#define	MXC_F_SPI_INT_FL_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_OVR_POS))

#define	MXC_F_SPI_INT_FL_TX_UND_POS 13

#define	MXC_F_SPI_INT_FL_TX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_UND_POS))

#define	MXC_F_SPI_INT_FL_RX_OVR_POS 14

#define	MXC_F_SPI_INT_FL_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_OVR_POS))

#define	MXC_F_SPI_INT_FL_RX_UND_POS 15

#define	MXC_F_SPI_INT_FL_RX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_UND_POS))

Detailed Description

Register for reading and clearing interrupt flags. All bits are write 1 to clear.

Macro Definition Documentation

◆ MXC_F_SPI_INT_FL_ABORT

#define MXC_F_SPI_INT_FL_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_ABORT_POS))

INT_FL_ABORT Mask

◆ MXC_F_SPI_INT_FL_ABORT_POS

#define MXC_F_SPI_INT_FL_ABORT_POS 9

INT_FL_ABORT Position

◆ MXC_F_SPI_INT_FL_FAULT

#define MXC_F_SPI_INT_FL_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_FAULT_POS))

INT_FL_FAULT Mask

◆ MXC_F_SPI_INT_FL_FAULT_POS

#define MXC_F_SPI_INT_FL_FAULT_POS 8

INT_FL_FAULT Position

◆ MXC_F_SPI_INT_FL_M_DONE

#define MXC_F_SPI_INT_FL_M_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_M_DONE_POS))

INT_FL_M_DONE Mask

◆ MXC_F_SPI_INT_FL_M_DONE_POS

#define MXC_F_SPI_INT_FL_M_DONE_POS 11

INT_FL_M_DONE Position

◆ MXC_F_SPI_INT_FL_RX_FULL

#define MXC_F_SPI_INT_FL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_FULL_POS))

INT_FL_RX_FULL Mask

◆ MXC_F_SPI_INT_FL_RX_FULL_POS

#define MXC_F_SPI_INT_FL_RX_FULL_POS 3

INT_FL_RX_FULL Position

◆ MXC_F_SPI_INT_FL_RX_OVR

#define MXC_F_SPI_INT_FL_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_OVR_POS))

INT_FL_RX_OVR Mask

◆ MXC_F_SPI_INT_FL_RX_OVR_POS

#define MXC_F_SPI_INT_FL_RX_OVR_POS 14

INT_FL_RX_OVR Position

◆ MXC_F_SPI_INT_FL_RX_THRESH

#define MXC_F_SPI_INT_FL_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_THRESH_POS))

INT_FL_RX_THRESH Mask

◆ MXC_F_SPI_INT_FL_RX_THRESH_POS

#define MXC_F_SPI_INT_FL_RX_THRESH_POS 2

INT_FL_RX_THRESH Position

◆ MXC_F_SPI_INT_FL_RX_UND

#define MXC_F_SPI_INT_FL_RX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_RX_UND_POS))

INT_FL_RX_UND Mask

◆ MXC_F_SPI_INT_FL_RX_UND_POS

#define MXC_F_SPI_INT_FL_RX_UND_POS 15

INT_FL_RX_UND Position

◆ MXC_F_SPI_INT_FL_SSA

#define MXC_F_SPI_INT_FL_SSA ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_SSA_POS))

INT_FL_SSA Mask

◆ MXC_F_SPI_INT_FL_SSA_POS

#define MXC_F_SPI_INT_FL_SSA_POS 4

INT_FL_SSA Position

◆ MXC_F_SPI_INT_FL_SSD

#define MXC_F_SPI_INT_FL_SSD ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_SSD_POS))

INT_FL_SSD Mask

◆ MXC_F_SPI_INT_FL_SSD_POS

#define MXC_F_SPI_INT_FL_SSD_POS 5

INT_FL_SSD Position

◆ MXC_F_SPI_INT_FL_TX_EMPTY

#define MXC_F_SPI_INT_FL_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_EMPTY_POS))

INT_FL_TX_EMPTY Mask

◆ MXC_F_SPI_INT_FL_TX_EMPTY_POS

#define MXC_F_SPI_INT_FL_TX_EMPTY_POS 1

INT_FL_TX_EMPTY Position

◆ MXC_F_SPI_INT_FL_TX_OVR

#define MXC_F_SPI_INT_FL_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_OVR_POS))

INT_FL_TX_OVR Mask

◆ MXC_F_SPI_INT_FL_TX_OVR_POS

#define MXC_F_SPI_INT_FL_TX_OVR_POS 12

INT_FL_TX_OVR Position

◆ MXC_F_SPI_INT_FL_TX_THRESH

#define MXC_F_SPI_INT_FL_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_THRESH_POS))

INT_FL_TX_THRESH Mask

◆ MXC_F_SPI_INT_FL_TX_THRESH_POS

#define MXC_F_SPI_INT_FL_TX_THRESH_POS 0

INT_FL_TX_THRESH Position

◆ MXC_F_SPI_INT_FL_TX_UND

#define MXC_F_SPI_INT_FL_TX_UND ((uint32_t)(0x1UL << MXC_F_SPI_INT_FL_TX_UND_POS))

INT_FL_TX_UND Mask

◆ MXC_F_SPI_INT_FL_TX_UND_POS

#define MXC_F_SPI_INT_FL_TX_UND_POS 13

INT_FL_TX_UND Position

Macros