Register Offsets

Macros
#define	MXC_R_SRCC_CACHE_ID   ((uint32_t)0x00000000UL)
#define	MXC_R_SRCC_MEMCFG   ((uint32_t)0x00000004UL)
#define	MXC_R_SRCC_CACHE_CTRL   ((uint32_t)0x00000100UL)
#define	MXC_R_SRCC_INVALIDATE   ((uint32_t)0x00000700UL)

Detailed Description

SRCC Peripheral Register Offsets from the SRCC Base Peripheral Address.

Macro Definition Documentation

MXC_R_SRCC_CACHE_CTRL

#define MXC_R_SRCC_CACHE_CTRL   ((uint32_t)0x00000100UL)

Offset from SRCC Base Address: 0x0100

MXC_R_SRCC_CACHE_ID

#define MXC_R_SRCC_CACHE_ID   ((uint32_t)0x00000000UL)

Offset from SRCC Base Address: 0x0000

MXC_R_SRCC_INVALIDATE

#define MXC_R_SRCC_INVALIDATE   ((uint32_t)0x00000700UL)

Offset from SRCC Base Address: 0x0700

MXC_R_SRCC_MEMCFG

#define MXC_R_SRCC_MEMCFG   ((uint32_t)0x00000004UL)

Offset from SRCC Base Address: 0x0004