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MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
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Macros | |
#define | MXC_F_TRNG_CN_ODHT_POS 0 |
#define | MXC_F_TRNG_CN_ODHT ((uint32_t)(0x1UL << MXC_F_TRNG_CN_ODHT_POS)) |
#define | MXC_F_TRNG_CN_RND_IRQ_EN_POS 1 |
#define | MXC_F_TRNG_CN_RND_IRQ_EN ((uint32_t)(0x1UL << MXC_F_TRNG_CN_RND_IRQ_EN_POS)) |
#define | MXC_F_TRNG_CN_HEALTH_EN_POS 2 |
#define | MXC_F_TRNG_CN_HEALTH_EN ((uint32_t)(0x1UL << MXC_F_TRNG_CN_HEALTH_EN_POS)) |
#define | MXC_F_TRNG_CN_AESKG_MEU_POS 3 |
#define | MXC_F_TRNG_CN_AESKG_MEU ((uint32_t)(0x1UL << MXC_F_TRNG_CN_AESKG_MEU_POS)) |
#define | MXC_F_TRNG_CN_AESKG_MEMPROTE_POS 4 |
#define | MXC_F_TRNG_CN_AESKG_MEMPROTE ((uint32_t)(0x1UL << MXC_F_TRNG_CN_AESKG_MEMPROTE_POS)) |
#define | MXC_F_TRNG_CN_AESKG_MEMPROTA_POS 5 |
#define | MXC_F_TRNG_CN_AESKG_MEMPROTA ((uint32_t)(0x1UL << MXC_F_TRNG_CN_AESKG_MEMPROTA_POS)) |
TRNG Control Register.
#define MXC_F_TRNG_CN_AESKG_MEMPROTA ((uint32_t)(0x1UL << MXC_F_TRNG_CN_AESKG_MEMPROTA_POS)) |
CN_AESKG_MEMPROTA Mask
#define MXC_F_TRNG_CN_AESKG_MEMPROTA_POS 5 |
CN_AESKG_MEMPROTA Position
#define MXC_F_TRNG_CN_AESKG_MEMPROTE ((uint32_t)(0x1UL << MXC_F_TRNG_CN_AESKG_MEMPROTE_POS)) |
CN_AESKG_MEMPROTE Mask
#define MXC_F_TRNG_CN_AESKG_MEMPROTE_POS 4 |
CN_AESKG_MEMPROTE Position
#define MXC_F_TRNG_CN_AESKG_MEU ((uint32_t)(0x1UL << MXC_F_TRNG_CN_AESKG_MEU_POS)) |
CN_AESKG_MEU Mask
#define MXC_F_TRNG_CN_AESKG_MEU_POS 3 |
CN_AESKG_MEU Position
#define MXC_F_TRNG_CN_HEALTH_EN ((uint32_t)(0x1UL << MXC_F_TRNG_CN_HEALTH_EN_POS)) |
CN_HEALTH_EN Mask
#define MXC_F_TRNG_CN_HEALTH_EN_POS 2 |
CN_HEALTH_EN Position
#define MXC_F_TRNG_CN_ODHT ((uint32_t)(0x1UL << MXC_F_TRNG_CN_ODHT_POS)) |
CN_ODHT Mask
#define MXC_F_TRNG_CN_ODHT_POS 0 |
CN_ODHT Position
#define MXC_F_TRNG_CN_RND_IRQ_EN ((uint32_t)(0x1UL << MXC_F_TRNG_CN_RND_IRQ_EN_POS)) |
CN_RND_IRQ_EN Mask
#define MXC_F_TRNG_CN_RND_IRQ_EN_POS 1 |
CN_RND_IRQ_EN Position