TRNG_ST

Macros
#define	MXC_F_TRNG_ST_RND_RDY_POS   0
#define	MXC_F_TRNG_ST_RND_RDY   ((uint32_t)(0x1UL << MXC_F_TRNG_ST_RND_RDY_POS))
#define	MXC_F_TRNG_ST_ODHTS_POS   1
#define	MXC_F_TRNG_ST_ODHTS   ((uint32_t)(0x1UL << MXC_F_TRNG_ST_ODHTS_POS))
#define	MXC_F_TRNG_ST_HTS_POS   2
#define	MXC_F_TRNG_ST_HTS   ((uint32_t)(0x1UL << MXC_F_TRNG_ST_HTS_POS))
#define	MXC_F_TRNG_ST_SRCFAIL_POS   3
#define	MXC_F_TRNG_ST_SRCFAIL   ((uint32_t)(0x1UL << MXC_F_TRNG_ST_SRCFAIL_POS))
#define	MXC_F_TRNG_ST_AESKGD_MEU_S_POS   4
#define	MXC_F_TRNG_ST_AESKGD_MEU_S   ((uint32_t)(0x1UL << MXC_F_TRNG_ST_AESKGD_MEU_S_POS))

Detailed Description

Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000.

Macro Definition Documentation

MXC_F_TRNG_ST_AESKGD_MEU_S

#define MXC_F_TRNG_ST_AESKGD_MEU_S   ((uint32_t)(0x1UL << MXC_F_TRNG_ST_AESKGD_MEU_S_POS))

ST_AESKGD_MEU_S Mask

MXC_F_TRNG_ST_AESKGD_MEU_S_POS

#define MXC_F_TRNG_ST_AESKGD_MEU_S_POS   4

ST_AESKGD_MEU_S Position

MXC_F_TRNG_ST_HTS

#define MXC_F_TRNG_ST_HTS   ((uint32_t)(0x1UL << MXC_F_TRNG_ST_HTS_POS))

ST_HTS Mask

MXC_F_TRNG_ST_HTS_POS

#define MXC_F_TRNG_ST_HTS_POS   2

ST_HTS Position

MXC_F_TRNG_ST_ODHTS

#define MXC_F_TRNG_ST_ODHTS   ((uint32_t)(0x1UL << MXC_F_TRNG_ST_ODHTS_POS))

ST_ODHTS Mask

MXC_F_TRNG_ST_ODHTS_POS

#define MXC_F_TRNG_ST_ODHTS_POS   1

ST_ODHTS Position

MXC_F_TRNG_ST_RND_RDY

#define MXC_F_TRNG_ST_RND_RDY   ((uint32_t)(0x1UL << MXC_F_TRNG_ST_RND_RDY_POS))

ST_RND_RDY Mask

MXC_F_TRNG_ST_RND_RDY_POS

#define MXC_F_TRNG_ST_RND_RDY_POS   0

ST_RND_RDY Position

MXC_F_TRNG_ST_SRCFAIL

#define MXC_F_TRNG_ST_SRCFAIL   ((uint32_t)(0x1UL << MXC_F_TRNG_ST_SRCFAIL_POS))

ST_SRCFAIL Mask

MXC_F_TRNG_ST_SRCFAIL_POS

#define MXC_F_TRNG_ST_SRCFAIL_POS   3

ST_SRCFAIL Position