MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
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Macros
Register Offsets
USBHS_Registers

Macros

#define MXC_R_USBHS_FADDR   ((uint32_t)0x00000000UL)
 
#define MXC_R_USBHS_POWER   ((uint32_t)0x00000001UL)
 
#define MXC_R_USBHS_INTRIN   ((uint32_t)0x00000002UL)
 
#define MXC_R_USBHS_INTROUT   ((uint32_t)0x00000004UL)
 
#define MXC_R_USBHS_INTRINEN   ((uint32_t)0x00000006UL)
 
#define MXC_R_USBHS_INTROUTEN   ((uint32_t)0x00000008UL)
 
#define MXC_R_USBHS_INTRUSB   ((uint32_t)0x0000000AUL)
 
#define MXC_R_USBHS_INTRUSBEN   ((uint32_t)0x0000000BUL)
 
#define MXC_R_USBHS_FRAME   ((uint32_t)0x0000000CUL)
 
#define MXC_R_USBHS_INDEX   ((uint32_t)0x0000000EUL)
 
#define MXC_R_USBHS_TESTMODE   ((uint32_t)0x0000000FUL)
 
#define MXC_R_USBHS_INMAXP   ((uint32_t)0x00000010UL)
 
#define MXC_R_USBHS_CSR0   ((uint32_t)0x00000012UL)
 
#define MXC_R_USBHS_INCSRL   ((uint32_t)0x00000012UL)
 
#define MXC_R_USBHS_INCSRU   ((uint32_t)0x00000013UL)
 
#define MXC_R_USBHS_OUTMAXP   ((uint32_t)0x00000014UL)
 
#define MXC_R_USBHS_OUTCSRL   ((uint32_t)0x00000016UL)
 
#define MXC_R_USBHS_OUTCSRU   ((uint32_t)0x00000017UL)
 
#define MXC_R_USBHS_COUNT0   ((uint32_t)0x00000018UL)
 
#define MXC_R_USBHS_OUTCOUNT   ((uint32_t)0x00000018UL)
 
#define MXC_R_USBHS_FIFO0   ((uint32_t)0x00000020UL)
 
#define MXC_R_USBHS_FIFO1   ((uint32_t)0x00000024UL)
 
#define MXC_R_USBHS_FIFO2   ((uint32_t)0x00000028UL)
 
#define MXC_R_USBHS_FIFO3   ((uint32_t)0x0000002CUL)
 
#define MXC_R_USBHS_FIFO4   ((uint32_t)0x00000030UL)
 
#define MXC_R_USBHS_FIFO5   ((uint32_t)0x00000034UL)
 
#define MXC_R_USBHS_FIFO6   ((uint32_t)0x00000038UL)
 
#define MXC_R_USBHS_FIFO7   ((uint32_t)0x0000003CUL)
 
#define MXC_R_USBHS_FIFO8   ((uint32_t)0x00000040UL)
 
#define MXC_R_USBHS_FIFO9   ((uint32_t)0x00000044UL)
 
#define MXC_R_USBHS_FIFO10   ((uint32_t)0x00000048UL)
 
#define MXC_R_USBHS_FIFO11   ((uint32_t)0x0000004CUL)
 
#define MXC_R_USBHS_FIFO12   ((uint32_t)0x00000050UL)
 
#define MXC_R_USBHS_FIFO13   ((uint32_t)0x00000054UL)
 
#define MXC_R_USBHS_FIFO14   ((uint32_t)0x00000058UL)
 
#define MXC_R_USBHS_FIFO15   ((uint32_t)0x0000005CUL)
 
#define MXC_R_USBHS_HWVERS   ((uint32_t)0x0000006CUL)
 
#define MXC_R_USBHS_EPINFO   ((uint32_t)0x00000078UL)
 
#define MXC_R_USBHS_RAMINFO   ((uint32_t)0x00000079UL)
 
#define MXC_R_USBHS_SOFTRESET   ((uint32_t)0x0000007AUL)
 
#define MXC_R_USBHS_CTUCH   ((uint32_t)0x00000080UL)
 
#define MXC_R_USBHS_CTHSRTN   ((uint32_t)0x00000082UL)
 
#define MXC_R_USBHS_MXM_USB_REG_00   ((uint32_t)0x00000400UL)
 
#define MXC_R_USBHS_M31_PHY_UTMI_RESET   ((uint32_t)0x00000404UL)
 
#define MXC_R_USBHS_M31_PHY_UTMI_VCONTROL   ((uint32_t)0x00000408UL)
 
#define MXC_R_USBHS_M31_PHY_CLK_EN   ((uint32_t)0x0000040CUL)
 
#define MXC_R_USBHS_M31_PHY_PONRST   ((uint32_t)0x00000410UL)
 
#define MXC_R_USBHS_M31_PHY_NONCRY_RSTB   ((uint32_t)0x00000414UL)
 
#define MXC_R_USBHS_M31_PHY_NONCRY_EN   ((uint32_t)0x00000418UL)
 
#define MXC_R_USBHS_M31_PHY_U2_COMPLIANCE_EN   ((uint32_t)0x00000420UL)
 
#define MXC_R_USBHS_M31_PHY_U2_COMPLIANCE_DAC_ADJ   ((uint32_t)0x00000424UL)
 
#define MXC_R_USBHS_M31_PHY_U2_COMPLIANCE_DAC_ADJ_EN   ((uint32_t)0x00000428UL)
 
#define MXC_R_USBHS_M31_PHY_CLK_RDY   ((uint32_t)0x0000042CUL)
 
#define MXC_R_USBHS_M31_PHY_PLL_EN   ((uint32_t)0x00000430UL)
 
#define MXC_R_USBHS_M31_PHY_BIST_OK   ((uint32_t)0x00000434UL)
 
#define MXC_R_USBHS_M31_PHY_DATA_OE   ((uint32_t)0x00000438UL)
 
#define MXC_R_USBHS_M31_PHY_OSCOUTEN   ((uint32_t)0x0000043CUL)
 
#define MXC_R_USBHS_M31_PHY_LPM_ALIVE   ((uint32_t)0x00000440UL)
 
#define MXC_R_USBHS_M31_PHY_HS_BIST_MODE   ((uint32_t)0x00000444UL)
 
#define MXC_R_USBHS_M31_PHY_CORECLKIN   ((uint32_t)0x00000448UL)
 
#define MXC_R_USBHS_M31_PHY_XTLSEL   ((uint32_t)0x0000044CUL)
 
#define MXC_R_USBHS_M31_PHY_LS_EN   ((uint32_t)0x00000450UL)
 
#define MXC_R_USBHS_M31_PHY_DEBUG_SEL   ((uint32_t)0x00000454UL)
 
#define MXC_R_USBHS_M31_PHY_DEBUG_OUT   ((uint32_t)0x00000458UL)
 
#define MXC_R_USBHS_M31_PHY_OUTCLKSEL   ((uint32_t)0x0000045CUL)
 
#define MXC_R_USBHS_M31_PHY_XCFGI_31_0   ((uint32_t)0x00000460UL)
 
#define MXC_R_USBHS_M31_PHY_XCFGI_63_32   ((uint32_t)0x00000464UL)
 
#define MXC_R_USBHS_M31_PHY_XCFGI_95_64   ((uint32_t)0x00000468UL)
 
#define MXC_R_USBHS_M31_PHY_XCFGI_127_96   ((uint32_t)0x0000046CUL)
 
#define MXC_R_USBHS_M31_PHY_XCFGI_137_128   ((uint32_t)0x00000470UL)
 
#define MXC_R_USBHS_M31_PHY_XCFG_HS_COARSE_TUNE_NUM   ((uint32_t)0x00000474UL)
 
#define MXC_R_USBHS_M31_PHY_XCFG_HS_FINE_TUNE_NUM   ((uint32_t)0x00000478UL)
 
#define MXC_R_USBHS_M31_PHY_XCFG_FS_COARSE_TUNE_NUM   ((uint32_t)0x0000047CUL)
 
#define MXC_R_USBHS_M31_PHY_XCFG_FS_FINE_TUNE_NUM   ((uint32_t)0x00000480UL)
 
#define MXC_R_USBHS_M31_PHY_XCFG_LOCK_RANGE_MAX   ((uint32_t)0x00000484UL)
 
#define MXC_R_USBHS_M31_PHY_XCFGI_LOCK_RANGE_MIN   ((uint32_t)0x00000488UL)
 
#define MXC_R_USBHS_M31_PHY_XCFG_OB_RSEL   ((uint32_t)0x0000048CUL)
 
#define MXC_R_USBHS_M31_PHY_XCFG_OC_RSEL   ((uint32_t)0x00000490UL)
 
#define MXC_R_USBHS_M31_PHY_XCFGO   ((uint32_t)0x00000494UL)
 
#define MXC_R_USBHS_MXM_INT   ((uint32_t)0x00000498UL)
 
#define MXC_R_USBHS_MXM_INT_EN   ((uint32_t)0x0000049CUL)
 
#define MXC_R_USBHS_MXM_SUSPEND   ((uint32_t)0x000004A0UL)
 
#define MXC_R_USBHS_MXM_REG_A4   ((uint32_t)0x000004A4UL)
 

Detailed Description

USBHS Peripheral Register Offsets from the USBHS Base Peripheral Address.

Macro Definition Documentation

◆ MXC_R_USBHS_COUNT0

#define MXC_R_USBHS_COUNT0   ((uint32_t)0x00000018UL)

Offset from USBHS Base Address: 0x0018

◆ MXC_R_USBHS_CSR0

#define MXC_R_USBHS_CSR0   ((uint32_t)0x00000012UL)

Offset from USBHS Base Address: 0x0012

◆ MXC_R_USBHS_CTHSRTN

#define MXC_R_USBHS_CTHSRTN   ((uint32_t)0x00000082UL)

Offset from USBHS Base Address: 0x0082

◆ MXC_R_USBHS_CTUCH

#define MXC_R_USBHS_CTUCH   ((uint32_t)0x00000080UL)

Offset from USBHS Base Address: 0x0080

◆ MXC_R_USBHS_EPINFO

#define MXC_R_USBHS_EPINFO   ((uint32_t)0x00000078UL)

Offset from USBHS Base Address: 0x0078

◆ MXC_R_USBHS_FADDR

#define MXC_R_USBHS_FADDR   ((uint32_t)0x00000000UL)

Offset from USBHS Base Address: 0x0000

◆ MXC_R_USBHS_FIFO0

#define MXC_R_USBHS_FIFO0   ((uint32_t)0x00000020UL)

Offset from USBHS Base Address: 0x0020

◆ MXC_R_USBHS_FIFO1

#define MXC_R_USBHS_FIFO1   ((uint32_t)0x00000024UL)

Offset from USBHS Base Address: 0x0024

◆ MXC_R_USBHS_FIFO10

#define MXC_R_USBHS_FIFO10   ((uint32_t)0x00000048UL)

Offset from USBHS Base Address: 0x0048

◆ MXC_R_USBHS_FIFO11

#define MXC_R_USBHS_FIFO11   ((uint32_t)0x0000004CUL)

Offset from USBHS Base Address: 0x004C

◆ MXC_R_USBHS_FIFO12

#define MXC_R_USBHS_FIFO12   ((uint32_t)0x00000050UL)

Offset from USBHS Base Address: 0x0050

◆ MXC_R_USBHS_FIFO13

#define MXC_R_USBHS_FIFO13   ((uint32_t)0x00000054UL)

Offset from USBHS Base Address: 0x0054

◆ MXC_R_USBHS_FIFO14

#define MXC_R_USBHS_FIFO14   ((uint32_t)0x00000058UL)

Offset from USBHS Base Address: 0x0058

◆ MXC_R_USBHS_FIFO15

#define MXC_R_USBHS_FIFO15   ((uint32_t)0x0000005CUL)

Offset from USBHS Base Address: 0x005C

◆ MXC_R_USBHS_FIFO2

#define MXC_R_USBHS_FIFO2   ((uint32_t)0x00000028UL)

Offset from USBHS Base Address: 0x0028

◆ MXC_R_USBHS_FIFO3

#define MXC_R_USBHS_FIFO3   ((uint32_t)0x0000002CUL)

Offset from USBHS Base Address: 0x002C

◆ MXC_R_USBHS_FIFO4

#define MXC_R_USBHS_FIFO4   ((uint32_t)0x00000030UL)

Offset from USBHS Base Address: 0x0030

◆ MXC_R_USBHS_FIFO5

#define MXC_R_USBHS_FIFO5   ((uint32_t)0x00000034UL)

Offset from USBHS Base Address: 0x0034

◆ MXC_R_USBHS_FIFO6

#define MXC_R_USBHS_FIFO6   ((uint32_t)0x00000038UL)

Offset from USBHS Base Address: 0x0038

◆ MXC_R_USBHS_FIFO7

#define MXC_R_USBHS_FIFO7   ((uint32_t)0x0000003CUL)

Offset from USBHS Base Address: 0x003C

◆ MXC_R_USBHS_FIFO8

#define MXC_R_USBHS_FIFO8   ((uint32_t)0x00000040UL)

Offset from USBHS Base Address: 0x0040

◆ MXC_R_USBHS_FIFO9

#define MXC_R_USBHS_FIFO9   ((uint32_t)0x00000044UL)

Offset from USBHS Base Address: 0x0044

◆ MXC_R_USBHS_FRAME

#define MXC_R_USBHS_FRAME   ((uint32_t)0x0000000CUL)

Offset from USBHS Base Address: 0x000C

◆ MXC_R_USBHS_HWVERS

#define MXC_R_USBHS_HWVERS   ((uint32_t)0x0000006CUL)

Offset from USBHS Base Address: 0x006C

◆ MXC_R_USBHS_INCSRL

#define MXC_R_USBHS_INCSRL   ((uint32_t)0x00000012UL)

Offset from USBHS Base Address: 0x0012

◆ MXC_R_USBHS_INCSRU

#define MXC_R_USBHS_INCSRU   ((uint32_t)0x00000013UL)

Offset from USBHS Base Address: 0x0013

◆ MXC_R_USBHS_INDEX

#define MXC_R_USBHS_INDEX   ((uint32_t)0x0000000EUL)

Offset from USBHS Base Address: 0x000E

◆ MXC_R_USBHS_INMAXP

#define MXC_R_USBHS_INMAXP   ((uint32_t)0x00000010UL)

Offset from USBHS Base Address: 0x0010

◆ MXC_R_USBHS_INTRIN

#define MXC_R_USBHS_INTRIN   ((uint32_t)0x00000002UL)

Offset from USBHS Base Address: 0x0002

◆ MXC_R_USBHS_INTRINEN

#define MXC_R_USBHS_INTRINEN   ((uint32_t)0x00000006UL)

Offset from USBHS Base Address: 0x0006

◆ MXC_R_USBHS_INTROUT

#define MXC_R_USBHS_INTROUT   ((uint32_t)0x00000004UL)

Offset from USBHS Base Address: 0x0004

◆ MXC_R_USBHS_INTROUTEN

#define MXC_R_USBHS_INTROUTEN   ((uint32_t)0x00000008UL)

Offset from USBHS Base Address: 0x0008

◆ MXC_R_USBHS_INTRUSB

#define MXC_R_USBHS_INTRUSB   ((uint32_t)0x0000000AUL)

Offset from USBHS Base Address: 0x000A

◆ MXC_R_USBHS_INTRUSBEN

#define MXC_R_USBHS_INTRUSBEN   ((uint32_t)0x0000000BUL)

Offset from USBHS Base Address: 0x000B

◆ MXC_R_USBHS_M31_PHY_BIST_OK

#define MXC_R_USBHS_M31_PHY_BIST_OK   ((uint32_t)0x00000434UL)

Offset from USBHS Base Address: 0x0434

◆ MXC_R_USBHS_M31_PHY_CLK_EN

#define MXC_R_USBHS_M31_PHY_CLK_EN   ((uint32_t)0x0000040CUL)

Offset from USBHS Base Address: 0x040C

◆ MXC_R_USBHS_M31_PHY_CLK_RDY

#define MXC_R_USBHS_M31_PHY_CLK_RDY   ((uint32_t)0x0000042CUL)

Offset from USBHS Base Address: 0x042C

◆ MXC_R_USBHS_M31_PHY_CORECLKIN

#define MXC_R_USBHS_M31_PHY_CORECLKIN   ((uint32_t)0x00000448UL)

Offset from USBHS Base Address: 0x0448

◆ MXC_R_USBHS_M31_PHY_DATA_OE

#define MXC_R_USBHS_M31_PHY_DATA_OE   ((uint32_t)0x00000438UL)

Offset from USBHS Base Address: 0x0438

◆ MXC_R_USBHS_M31_PHY_DEBUG_OUT

#define MXC_R_USBHS_M31_PHY_DEBUG_OUT   ((uint32_t)0x00000458UL)

Offset from USBHS Base Address: 0x0458

◆ MXC_R_USBHS_M31_PHY_DEBUG_SEL

#define MXC_R_USBHS_M31_PHY_DEBUG_SEL   ((uint32_t)0x00000454UL)

Offset from USBHS Base Address: 0x0454

◆ MXC_R_USBHS_M31_PHY_HS_BIST_MODE

#define MXC_R_USBHS_M31_PHY_HS_BIST_MODE   ((uint32_t)0x00000444UL)

Offset from USBHS Base Address: 0x0444

◆ MXC_R_USBHS_M31_PHY_LPM_ALIVE

#define MXC_R_USBHS_M31_PHY_LPM_ALIVE   ((uint32_t)0x00000440UL)

Offset from USBHS Base Address: 0x0440

◆ MXC_R_USBHS_M31_PHY_LS_EN

#define MXC_R_USBHS_M31_PHY_LS_EN   ((uint32_t)0x00000450UL)

Offset from USBHS Base Address: 0x0450

◆ MXC_R_USBHS_M31_PHY_NONCRY_EN

#define MXC_R_USBHS_M31_PHY_NONCRY_EN   ((uint32_t)0x00000418UL)

Offset from USBHS Base Address: 0x0418

◆ MXC_R_USBHS_M31_PHY_NONCRY_RSTB

#define MXC_R_USBHS_M31_PHY_NONCRY_RSTB   ((uint32_t)0x00000414UL)

Offset from USBHS Base Address: 0x0414

◆ MXC_R_USBHS_M31_PHY_OSCOUTEN

#define MXC_R_USBHS_M31_PHY_OSCOUTEN   ((uint32_t)0x0000043CUL)

Offset from USBHS Base Address: 0x043C

◆ MXC_R_USBHS_M31_PHY_OUTCLKSEL

#define MXC_R_USBHS_M31_PHY_OUTCLKSEL   ((uint32_t)0x0000045CUL)

Offset from USBHS Base Address: 0x045C

◆ MXC_R_USBHS_M31_PHY_PLL_EN

#define MXC_R_USBHS_M31_PHY_PLL_EN   ((uint32_t)0x00000430UL)

Offset from USBHS Base Address: 0x0430

◆ MXC_R_USBHS_M31_PHY_PONRST

#define MXC_R_USBHS_M31_PHY_PONRST   ((uint32_t)0x00000410UL)

Offset from USBHS Base Address: 0x0410

◆ MXC_R_USBHS_M31_PHY_U2_COMPLIANCE_DAC_ADJ

#define MXC_R_USBHS_M31_PHY_U2_COMPLIANCE_DAC_ADJ   ((uint32_t)0x00000424UL)

Offset from USBHS Base Address: 0x0424

◆ MXC_R_USBHS_M31_PHY_U2_COMPLIANCE_DAC_ADJ_EN

#define MXC_R_USBHS_M31_PHY_U2_COMPLIANCE_DAC_ADJ_EN   ((uint32_t)0x00000428UL)

Offset from USBHS Base Address: 0x0428

◆ MXC_R_USBHS_M31_PHY_U2_COMPLIANCE_EN

#define MXC_R_USBHS_M31_PHY_U2_COMPLIANCE_EN   ((uint32_t)0x00000420UL)

Offset from USBHS Base Address: 0x0420

◆ MXC_R_USBHS_M31_PHY_UTMI_RESET

#define MXC_R_USBHS_M31_PHY_UTMI_RESET   ((uint32_t)0x00000404UL)

Offset from USBHS Base Address: 0x0404

◆ MXC_R_USBHS_M31_PHY_UTMI_VCONTROL

#define MXC_R_USBHS_M31_PHY_UTMI_VCONTROL   ((uint32_t)0x00000408UL)

Offset from USBHS Base Address: 0x0408

◆ MXC_R_USBHS_M31_PHY_XCFG_FS_COARSE_TUNE_NUM

#define MXC_R_USBHS_M31_PHY_XCFG_FS_COARSE_TUNE_NUM   ((uint32_t)0x0000047CUL)

Offset from USBHS Base Address: 0x047C

◆ MXC_R_USBHS_M31_PHY_XCFG_FS_FINE_TUNE_NUM

#define MXC_R_USBHS_M31_PHY_XCFG_FS_FINE_TUNE_NUM   ((uint32_t)0x00000480UL)

Offset from USBHS Base Address: 0x0480

◆ MXC_R_USBHS_M31_PHY_XCFG_HS_COARSE_TUNE_NUM

#define MXC_R_USBHS_M31_PHY_XCFG_HS_COARSE_TUNE_NUM   ((uint32_t)0x00000474UL)

Offset from USBHS Base Address: 0x0474

◆ MXC_R_USBHS_M31_PHY_XCFG_HS_FINE_TUNE_NUM

#define MXC_R_USBHS_M31_PHY_XCFG_HS_FINE_TUNE_NUM   ((uint32_t)0x00000478UL)

Offset from USBHS Base Address: 0x0478

◆ MXC_R_USBHS_M31_PHY_XCFG_LOCK_RANGE_MAX

#define MXC_R_USBHS_M31_PHY_XCFG_LOCK_RANGE_MAX   ((uint32_t)0x00000484UL)

Offset from USBHS Base Address: 0x0484

◆ MXC_R_USBHS_M31_PHY_XCFG_OB_RSEL

#define MXC_R_USBHS_M31_PHY_XCFG_OB_RSEL   ((uint32_t)0x0000048CUL)

Offset from USBHS Base Address: 0x048C

◆ MXC_R_USBHS_M31_PHY_XCFG_OC_RSEL

#define MXC_R_USBHS_M31_PHY_XCFG_OC_RSEL   ((uint32_t)0x00000490UL)

Offset from USBHS Base Address: 0x0490

◆ MXC_R_USBHS_M31_PHY_XCFGI_127_96

#define MXC_R_USBHS_M31_PHY_XCFGI_127_96   ((uint32_t)0x0000046CUL)

Offset from USBHS Base Address: 0x046C

◆ MXC_R_USBHS_M31_PHY_XCFGI_137_128

#define MXC_R_USBHS_M31_PHY_XCFGI_137_128   ((uint32_t)0x00000470UL)

Offset from USBHS Base Address: 0x0470

◆ MXC_R_USBHS_M31_PHY_XCFGI_31_0

#define MXC_R_USBHS_M31_PHY_XCFGI_31_0   ((uint32_t)0x00000460UL)

Offset from USBHS Base Address: 0x0460

◆ MXC_R_USBHS_M31_PHY_XCFGI_63_32

#define MXC_R_USBHS_M31_PHY_XCFGI_63_32   ((uint32_t)0x00000464UL)

Offset from USBHS Base Address: 0x0464

◆ MXC_R_USBHS_M31_PHY_XCFGI_95_64

#define MXC_R_USBHS_M31_PHY_XCFGI_95_64   ((uint32_t)0x00000468UL)

Offset from USBHS Base Address: 0x0468

◆ MXC_R_USBHS_M31_PHY_XCFGI_LOCK_RANGE_MIN

#define MXC_R_USBHS_M31_PHY_XCFGI_LOCK_RANGE_MIN   ((uint32_t)0x00000488UL)

Offset from USBHS Base Address: 0x0488

◆ MXC_R_USBHS_M31_PHY_XCFGO

#define MXC_R_USBHS_M31_PHY_XCFGO   ((uint32_t)0x00000494UL)

Offset from USBHS Base Address: 0x0494

◆ MXC_R_USBHS_M31_PHY_XTLSEL

#define MXC_R_USBHS_M31_PHY_XTLSEL   ((uint32_t)0x0000044CUL)

Offset from USBHS Base Address: 0x044C

◆ MXC_R_USBHS_MXM_INT

#define MXC_R_USBHS_MXM_INT   ((uint32_t)0x00000498UL)

Offset from USBHS Base Address: 0x0498

◆ MXC_R_USBHS_MXM_INT_EN

#define MXC_R_USBHS_MXM_INT_EN   ((uint32_t)0x0000049CUL)

Offset from USBHS Base Address: 0x049C

◆ MXC_R_USBHS_MXM_REG_A4

#define MXC_R_USBHS_MXM_REG_A4   ((uint32_t)0x000004A4UL)

Offset from USBHS Base Address: 0x04A4

◆ MXC_R_USBHS_MXM_SUSPEND

#define MXC_R_USBHS_MXM_SUSPEND   ((uint32_t)0x000004A0UL)

Offset from USBHS Base Address: 0x04A0

◆ MXC_R_USBHS_MXM_USB_REG_00

#define MXC_R_USBHS_MXM_USB_REG_00   ((uint32_t)0x00000400UL)

Offset from USBHS Base Address: 0x0400

◆ MXC_R_USBHS_OUTCOUNT

#define MXC_R_USBHS_OUTCOUNT   ((uint32_t)0x00000018UL)

Offset from USBHS Base Address: 0x0018

◆ MXC_R_USBHS_OUTCSRL

#define MXC_R_USBHS_OUTCSRL   ((uint32_t)0x00000016UL)

Offset from USBHS Base Address: 0x0016

◆ MXC_R_USBHS_OUTCSRU

#define MXC_R_USBHS_OUTCSRU   ((uint32_t)0x00000017UL)

Offset from USBHS Base Address: 0x0017

◆ MXC_R_USBHS_OUTMAXP

#define MXC_R_USBHS_OUTMAXP   ((uint32_t)0x00000014UL)

Offset from USBHS Base Address: 0x0014

◆ MXC_R_USBHS_POWER

#define MXC_R_USBHS_POWER   ((uint32_t)0x00000001UL)

Offset from USBHS Base Address: 0x0001

◆ MXC_R_USBHS_RAMINFO

#define MXC_R_USBHS_RAMINFO   ((uint32_t)0x00000079UL)

Offset from USBHS Base Address: 0x0079

◆ MXC_R_USBHS_SOFTRESET

#define MXC_R_USBHS_SOFTRESET   ((uint32_t)0x0000007AUL)

Offset from USBHS Base Address: 0x007A

◆ MXC_R_USBHS_TESTMODE

#define MXC_R_USBHS_TESTMODE   ((uint32_t)0x0000000FUL)

Offset from USBHS Base Address: 0x000F