MAX32665 Peripheral Driver API
Peripheral Driver API for the MAX32665
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TPU_Registers
Trust Protection Unit (TPU)

Modules

 Register Offsets
 
 TPU_CTRL
 
 TPU_CIPHER_CTRL
 
 TPU_HASH_CTRL
 
 TPU_CRC_CTRL
 
 TPU_DMA_SRC
 
 TPU_DMA_DST
 
 TPU_DMA_CNT
 
 TPU_MAA_CTRL
 
 TPU_DATA_IN
 
 TPU_DATA_OUT
 
 TPU_CRC_POLY
 
 TPU_CRC_VAL
 
 TPU_CRC_PRNG
 
 TPU_HAM_ECC
 
 TPU_CIPHER_INIT
 
 TPU_CIPHER_KEY
 
 TPU_HASH_DIGEST
 
 TPU_HASH_MSG_SZ
 
 TPU_MAA_MAWS
 

Files

file  tpu_regs.h
 

Data Structures

struct  mxc_tpu_regs_t
 

Detailed Description

Registers, Bit Masks and Bit Positions for the TPU Peripheral Module.

The Trust Protection Unit used to assist the computationally intensive operations of several common cryptographic algorithms.

Data Structure Documentation

◆ mxc_tpu_regs_t

struct mxc_tpu_regs_t

Structure type to access the TPU Registers.

Data Fields

__IO uint32_t ctrl
 
__IO uint32_t cipher_ctrl
 
__IO uint32_t hash_ctrl
 
__IO uint32_t crc_ctrl
 
__IO uint32_t dma_src
 
__IO uint32_t dma_dst
 
__IO uint32_t dma_cnt
 
__IO uint32_t maa_ctrl
 
__O uint32_t data_in [4]
 
__I uint32_t data_out [4]
 
__IO uint32_t crc_poly
 
__IO uint32_t crc_val
 
__I uint32_t crc_prng
 
__IO uint32_t ham_ecc
 
__IO uint32_t cipher_init [4]
 
__O uint32_t cipher_key [8]
 
__IO uint32_t hash_digest [16]
 
__IO uint32_t hash_msg_sz [4]
 
__IO uint32_t maa_maws
 

Field Documentation

◆ cipher_ctrl

__IO uint32_t cipher_ctrl

0x04: TPU CIPHER_CTRL Register

◆ cipher_init

__IO uint32_t cipher_init[4]

0x50: TPU CIPHER_INIT Register

◆ cipher_key

__O uint32_t cipher_key[8]

0x60: TPU CIPHER_KEY Register

◆ crc_ctrl

__IO uint32_t crc_ctrl

0x0C: TPU CRC_CTRL Register

◆ crc_poly

__IO uint32_t crc_poly

0x40: TPU CRC_POLY Register

◆ crc_prng

__I uint32_t crc_prng

0x48: TPU CRC_PRNG Register

◆ crc_val

__IO uint32_t crc_val

0x44: TPU CRC_VAL Register

◆ ctrl

__IO uint32_t ctrl

0x00: TPU CTRL Register

◆ data_in

__O uint32_t data_in[4]

0x20: TPU DATA_IN Register

◆ data_out

__I uint32_t data_out[4]

0x30: TPU DATA_OUT Register

◆ dma_cnt

__IO uint32_t dma_cnt

0x18: TPU DMA_CNT Register

◆ dma_dst

__IO uint32_t dma_dst

0x14: TPU DMA_DST Register

◆ dma_src

__IO uint32_t dma_src

0x10: TPU DMA_SRC Register

◆ ham_ecc

__IO uint32_t ham_ecc

0x4C: TPU HAM_ECC Register

◆ hash_ctrl

__IO uint32_t hash_ctrl

0x08: TPU HASH_CTRL Register

◆ hash_digest

__IO uint32_t hash_digest[16]

0x80: TPU HASH_DIGEST Register

◆ hash_msg_sz

__IO uint32_t hash_msg_sz[4]

0xC0: TPU HASH_MSG_SZ Register

◆ maa_ctrl

__IO uint32_t maa_ctrl

0x1C: TPU MAA_CTRL Register

◆ maa_maws

__IO uint32_t maa_maws

0xD0: TPU MAA_MAWS Register