simo_regs.h

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/******************************************************************************
 *
 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 
 * Analog Devices, Inc.),
 * Copyright (C) 2023-2024 Analog Devices, Inc.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 ******************************************************************************/
 
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_SIMO_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_SIMO_REGS_H_
 
/* **** Includes **** */
#include <stdint.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
#if defined (__ICCARM__)
  #pragma system_include
#endif
 
#if defined (__CC_ARM)
  #pragma anon_unions
#endif
/*
    If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I  volatile const
#endif
#ifndef __O
#define __O  volatile
#endif
#ifndef __R
#define __R  volatile const
#endif
 
/* **** Definitions **** */
 
typedef struct {
    __R  uint32_t rsv_0x0;
    __IO uint32_t vrego_a;              
    __IO uint32_t vrego_b;              
    __IO uint32_t vrego_c;              
    __IO uint32_t vrego_d;              
    __IO uint32_t ipka;                 
    __IO uint32_t ipkb;                 
    __IO uint32_t maxton;               
    __I  uint32_t iload_a;              
    __I  uint32_t iload_b;              
    __I  uint32_t iload_c;              
    __I  uint32_t iload_d;              
    __IO uint32_t buck_alert_thr_a;     
    __IO uint32_t buck_alert_thr_b;     
    __IO uint32_t buck_alert_thr_c;     
    __IO uint32_t buck_alert_thr_d;     
    __I  uint32_t buck_out_ready;       
    __I  uint32_t zero_cross_cal_a;     
    __I  uint32_t zero_cross_cal_b;     
    __I  uint32_t zero_cross_cal_c;     
    __I  uint32_t zero_cross_cal_d;     
} mxc_simo_regs_t;
 
/* Register offsets for module SIMO */
#define MXC_R_SIMO_VREGO_A                 ((uint32_t)0x00000004UL) 
#define MXC_R_SIMO_VREGO_B                 ((uint32_t)0x00000008UL) 
#define MXC_R_SIMO_VREGO_C                 ((uint32_t)0x0000000CUL) 
#define MXC_R_SIMO_VREGO_D                 ((uint32_t)0x00000010UL) 
#define MXC_R_SIMO_IPKA                    ((uint32_t)0x00000014UL) 
#define MXC_R_SIMO_IPKB                    ((uint32_t)0x00000018UL) 
#define MXC_R_SIMO_MAXTON                  ((uint32_t)0x0000001CUL) 
#define MXC_R_SIMO_ILOAD_A                 ((uint32_t)0x00000020UL) 
#define MXC_R_SIMO_ILOAD_B                 ((uint32_t)0x00000024UL) 
#define MXC_R_SIMO_ILOAD_C                 ((uint32_t)0x00000028UL) 
#define MXC_R_SIMO_ILOAD_D                 ((uint32_t)0x0000002CUL) 
#define MXC_R_SIMO_BUCK_ALERT_THR_A        ((uint32_t)0x00000030UL) 
#define MXC_R_SIMO_BUCK_ALERT_THR_B        ((uint32_t)0x00000034UL) 
#define MXC_R_SIMO_BUCK_ALERT_THR_C        ((uint32_t)0x00000038UL) 
#define MXC_R_SIMO_BUCK_ALERT_THR_D        ((uint32_t)0x0000003CUL) 
#define MXC_R_SIMO_BUCK_OUT_READY          ((uint32_t)0x00000040UL) 
#define MXC_R_SIMO_ZERO_CROSS_CAL_A        ((uint32_t)0x00000044UL) 
#define MXC_R_SIMO_ZERO_CROSS_CAL_B        ((uint32_t)0x00000048UL) 
#define MXC_R_SIMO_ZERO_CROSS_CAL_C        ((uint32_t)0x0000004CUL) 
#define MXC_R_SIMO_ZERO_CROSS_CAL_D        ((uint32_t)0x00000050UL) 
#define MXC_F_SIMO_VREGO_A_VSETA_POS                   0 
#define MXC_F_SIMO_VREGO_A_VSETA                       ((uint32_t)(0x7FUL << MXC_F_SIMO_VREGO_A_VSETA_POS)) 
#define MXC_F_SIMO_VREGO_A_RANGEA_POS                  7 
#define MXC_F_SIMO_VREGO_A_RANGEA                      ((uint32_t)(0x1UL << MXC_F_SIMO_VREGO_A_RANGEA_POS)) 
#define MXC_F_SIMO_VREGO_B_VSETB_POS                   0 
#define MXC_F_SIMO_VREGO_B_VSETB                       ((uint32_t)(0x7FUL << MXC_F_SIMO_VREGO_B_VSETB_POS)) 
#define MXC_F_SIMO_VREGO_B_RANGEB_POS                  7 
#define MXC_F_SIMO_VREGO_B_RANGEB                      ((uint32_t)(0x1UL << MXC_F_SIMO_VREGO_B_RANGEB_POS)) 
#define MXC_F_SIMO_VREGO_C_VSETC_POS                   0 
#define MXC_F_SIMO_VREGO_C_VSETC                       ((uint32_t)(0x7FUL << MXC_F_SIMO_VREGO_C_VSETC_POS)) 
#define MXC_F_SIMO_VREGO_C_RANGEC_POS                  7 
#define MXC_F_SIMO_VREGO_C_RANGEC                      ((uint32_t)(0x1UL << MXC_F_SIMO_VREGO_C_RANGEC_POS)) 
#define MXC_F_SIMO_VREGO_D_VSETD_POS                   0 
#define MXC_F_SIMO_VREGO_D_VSETD                       ((uint32_t)(0x7FUL << MXC_F_SIMO_VREGO_D_VSETD_POS)) 
#define MXC_F_SIMO_VREGO_D_RANGED_POS                  7 
#define MXC_F_SIMO_VREGO_D_RANGED                      ((uint32_t)(0x1UL << MXC_F_SIMO_VREGO_D_RANGED_POS)) 
#define MXC_F_SIMO_IPKA_IPKSETA_POS                    0 
#define MXC_F_SIMO_IPKA_IPKSETA                        ((uint32_t)(0xFUL << MXC_F_SIMO_IPKA_IPKSETA_POS)) 
#define MXC_F_SIMO_IPKA_IPKSETB_POS                    4 
#define MXC_F_SIMO_IPKA_IPKSETB                        ((uint32_t)(0xFUL << MXC_F_SIMO_IPKA_IPKSETB_POS)) 
#define MXC_F_SIMO_IPKB_IPKSETC_POS                    0 
#define MXC_F_SIMO_IPKB_IPKSETC                        ((uint32_t)(0xFUL << MXC_F_SIMO_IPKB_IPKSETC_POS)) 
#define MXC_F_SIMO_IPKB_IPKSETD_POS                    4 
#define MXC_F_SIMO_IPKB_IPKSETD                        ((uint32_t)(0xFUL << MXC_F_SIMO_IPKB_IPKSETD_POS)) 
#define MXC_F_SIMO_MAXTON_TONSET_POS                   0 
#define MXC_F_SIMO_MAXTON_TONSET                       ((uint32_t)(0xFUL << MXC_F_SIMO_MAXTON_TONSET_POS)) 
#define MXC_F_SIMO_ILOAD_A_ILOADA_POS                  0 
#define MXC_F_SIMO_ILOAD_A_ILOADA                      ((uint32_t)(0xFFUL << MXC_F_SIMO_ILOAD_A_ILOADA_POS)) 
#define MXC_F_SIMO_ILOAD_B_ILOADB_POS                  0 
#define MXC_F_SIMO_ILOAD_B_ILOADB                      ((uint32_t)(0xFFUL << MXC_F_SIMO_ILOAD_B_ILOADB_POS)) 
#define MXC_F_SIMO_ILOAD_C_ILOADC_POS                  0 
#define MXC_F_SIMO_ILOAD_C_ILOADC                      ((uint32_t)(0xFFUL << MXC_F_SIMO_ILOAD_C_ILOADC_POS)) 
#define MXC_F_SIMO_ILOAD_D_ILOADD_POS                  0 
#define MXC_F_SIMO_ILOAD_D_ILOADD                      ((uint32_t)(0xFFUL << MXC_F_SIMO_ILOAD_D_ILOADD_POS)) 
#define MXC_F_SIMO_BUCK_ALERT_THR_A_BUCKTHRA_POS       0 
#define MXC_F_SIMO_BUCK_ALERT_THR_A_BUCKTHRA           ((uint32_t)(0xFFUL << MXC_F_SIMO_BUCK_ALERT_THR_A_BUCKTHRA_POS)) 
#define MXC_F_SIMO_BUCK_ALERT_THR_B_BUCKTHRB_POS       0 
#define MXC_F_SIMO_BUCK_ALERT_THR_B_BUCKTHRB           ((uint32_t)(0xFFUL << MXC_F_SIMO_BUCK_ALERT_THR_B_BUCKTHRB_POS)) 
#define MXC_F_SIMO_BUCK_ALERT_THR_C_BUCKTHRC_POS       0 
#define MXC_F_SIMO_BUCK_ALERT_THR_C_BUCKTHRC           ((uint32_t)(0xFFUL << MXC_F_SIMO_BUCK_ALERT_THR_C_BUCKTHRC_POS)) 
#define MXC_F_SIMO_BUCK_ALERT_THR_D_BUCKTHRD_POS       0 
#define MXC_F_SIMO_BUCK_ALERT_THR_D_BUCKTHRD           ((uint32_t)(0xFFUL << MXC_F_SIMO_BUCK_ALERT_THR_D_BUCKTHRD_POS)) 
#define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYA_POS      0 
#define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYA          ((uint32_t)(0x1UL << MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYA_POS)) 
#define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYB_POS      1 
#define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYB          ((uint32_t)(0x1UL << MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYB_POS)) 
#define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYC_POS      2 
#define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYC          ((uint32_t)(0x1UL << MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYC_POS)) 
#define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYD_POS      3 
#define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYD          ((uint32_t)(0x1UL << MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYD_POS)) 
#define MXC_F_SIMO_ZERO_CROSS_CAL_A_ZXCALA_POS         0 
#define MXC_F_SIMO_ZERO_CROSS_CAL_A_ZXCALA             ((uint32_t)(0xFUL << MXC_F_SIMO_ZERO_CROSS_CAL_A_ZXCALA_POS)) 
#define MXC_F_SIMO_ZERO_CROSS_CAL_B_ZXCALB_POS         0 
#define MXC_F_SIMO_ZERO_CROSS_CAL_B_ZXCALB             ((uint32_t)(0xFUL << MXC_F_SIMO_ZERO_CROSS_CAL_B_ZXCALB_POS)) 
#define MXC_F_SIMO_ZERO_CROSS_CAL_C_ZXCALC_POS         0 
#define MXC_F_SIMO_ZERO_CROSS_CAL_C_ZXCALC             ((uint32_t)(0xFUL << MXC_F_SIMO_ZERO_CROSS_CAL_C_ZXCALC_POS)) 
#define MXC_F_SIMO_ZERO_CROSS_CAL_D_ZXCALD_POS         0 
#define MXC_F_SIMO_ZERO_CROSS_CAL_D_ZXCALD             ((uint32_t)(0xFUL << MXC_F_SIMO_ZERO_CROSS_CAL_D_ZXCALD_POS)) 
#ifdef __cplusplus
}
#endif
 
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_SIMO_REGS_H_