Here are the data structures with brief descriptions:

Cmxc_adc_conversion_req_t	Used to set up channel for conversion
Cmxc_adc_monitor_req_t	Used to set up a monitor to watch a channel
Cmxc_adc_regs_t
Cmxc_aes_key_regs_t
Cmxc_aeskeys_regs_t
Cmxc_dma_adv_config_t	The advanced configuration options, these are optional but could be needed in cases where multiple DMA channels are running concurrently or DMA is being used with low bandwidth peripherals
Cmxc_dma_ch_regs_t
Cmxc_dma_config_t	The basic configuration information to set up a DMA channel and prepare it for transfers
Cmxc_dma_srcdst_t	The information needed to complete a DMA transfer
Cmxc_dvs_regs_t
Cmxc_fcr_regs_t
Cmxc_flc_regs_t
Cmxc_gcr_regs_t
Cmxc_gpio_cfg_t	Structure type for configuring a GPIO port
Cmxc_gpio_regs_t
Cmxc_htmr_regs_t
Cmxc_i2c_regs_t
Cmxc_i2c_req_t	The information required to perform a complete I2C transaction as the bus master
Cmxc_icc_regs_t
Cmxc_mcr_regs_t
Cmxc_owm_cfg_t	Structure type for 1-Wire Master configuration
Cmxc_owm_regs_t
Cmxc_pt_cfg_t	Structure type for pulse train mode configuration
Cmxc_pt_regs_t
Cmxc_ptg_regs_t
Cmxc_pwrseq_regs_t
Cmxc_rpu_regs_t
Cmxc_rtc_regs_t
Cmxc_sdhc_cfg_t	Used to configure voltage and clock for sdhc interface
Cmxc_sdhc_cmd_cfg_t	Used to configure sdhc interface
Cmxc_sdhc_regs_t
Cmxc_sdma_regs_t
Cmxc_sema_regs_t
Cmxc_simo_regs_t
Cmxc_sir_regs_t
Cmxc_smon_regs_t
Cmxc_spi_regs_t
Cmxc_spi_req_t	The information required to perform a complete SPI transaction
Cmxc_spixf_cfg_t	MXC_SPIXF configuration type
Cmxc_spixf_req_t	MXC_SPIXF Transaction request
Cmxc_spixfc_fifo_regs_t
Cmxc_spixfc_regs_t
Cmxc_spixfm_regs_t
Cmxc_spixr_cfg_t	Configuration parameters of SPIXR
Cmxc_spixr_regs_t
Cmxc_srcc_regs_t
Cmxc_tmr_cfg_t	Timer Configuration
Cmxc_tmr_regs_t
Cmxc_tpu_regs_t
Cmxc_trimsir_regs_t
Cmxc_trng_regs_t
Cmxc_uart_regs_t
Cmxc_uart_req_t	The information required to perform a complete UART transaction
Cmxc_usbhs_regs_t
Cmxc_wdt_regs_t
Cmxc_wut_cfg_t	Wakeup Timer Configuration
Cmxc_wut_regs_t