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#define | MXC_R_SPIXR_DATA32 ((uint32_t)0x00000000UL) |
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#define | MXC_R_SPIXR_DATA16 ((uint32_t)0x00000000UL) |
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#define | MXC_R_SPIXR_DATA8 ((uint32_t)0x00000000UL) |
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#define | MXC_R_SPIXR_CTRL1 ((uint32_t)0x00000004UL) |
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#define | MXC_R_SPIXR_CTRL2 ((uint32_t)0x00000008UL) |
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#define | MXC_R_SPIXR_CTRL3 ((uint32_t)0x0000000CUL) |
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#define | MXC_R_SPIXR_CTRL4 ((uint32_t)0x00000010UL) |
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#define | MXC_R_SPIXR_BRG_CTRL ((uint32_t)0x00000014UL) |
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#define | MXC_R_SPIXR_DMA ((uint32_t)0x0000001CUL) |
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#define | MXC_R_SPIXR_IRQ ((uint32_t)0x00000020UL) |
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#define | MXC_R_SPIXR_IRQE ((uint32_t)0x00000024UL) |
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#define | MXC_R_SPIXR_WAKE ((uint32_t)0x00000028UL) |
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#define | MXC_R_SPIXR_WAKEE ((uint32_t)0x0000002CUL) |
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#define | MXC_R_SPIXR_STAT ((uint32_t)0x00000030UL) |
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#define | MXC_R_SPIXR_XMEM_CTRL ((uint32_t)0x00000034UL) |
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#define | MXC_F_SPIXR_DATA32_DATA_POS 0 |
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#define | MXC_F_SPIXR_DATA32_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SPIXR_DATA32_DATA_POS)) |
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#define | MXC_F_SPIXR_DATA16_DATA_POS 0 |
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#define | MXC_F_SPIXR_DATA16_DATA ((uint16_t)(0xFFFFUL << MXC_F_SPIXR_DATA16_DATA_POS)) |
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#define | MXC_F_SPIXR_DATA8_DATA_POS 0 |
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#define | MXC_F_SPIXR_DATA8_DATA ((uint8_t)(0xFFUL << MXC_F_SPIXR_DATA8_DATA_POS)) |
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#define | MXC_F_SPIXR_CTRL1_SPIEN_POS 0 |
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#define | MXC_F_SPIXR_CTRL1_SPIEN ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL1_SPIEN_POS)) |
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#define | MXC_F_SPIXR_CTRL1_MMEN_POS 1 |
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#define | MXC_F_SPIXR_CTRL1_MMEN ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL1_MMEN_POS)) |
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#define | MXC_F_SPIXR_CTRL1_TIMER_POS 2 |
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#define | MXC_F_SPIXR_CTRL1_TIMER ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL1_TIMER_POS)) |
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#define | MXC_F_SPIXR_CTRL1_FL_EN_POS 3 |
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#define | MXC_F_SPIXR_CTRL1_FL_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL1_FL_EN_POS)) |
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#define | MXC_F_SPIXR_CTRL1_SSIO_POS 4 |
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#define | MXC_F_SPIXR_CTRL1_SSIO ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL1_SSIO_POS)) |
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#define | MXC_F_SPIXR_CTRL1_TX_START_POS 5 |
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#define | MXC_F_SPIXR_CTRL1_TX_START ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL1_TX_START_POS)) |
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#define | MXC_F_SPIXR_CTRL1_SS_CTRL_POS 8 |
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#define | MXC_F_SPIXR_CTRL1_SS_CTRL ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL1_SS_CTRL_POS)) |
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#define | MXC_F_SPIXR_CTRL1_SS_POS 16 |
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#define | MXC_F_SPIXR_CTRL1_SS ((uint32_t)(0xFFUL << MXC_F_SPIXR_CTRL1_SS_POS)) |
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#define | MXC_V_SPIXR_CTRL1_SS_SS0 ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_CTRL1_SS_SS0 (MXC_V_SPIXR_CTRL1_SS_SS0 << MXC_F_SPIXR_CTRL1_SS_POS) |
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#define | MXC_V_SPIXR_CTRL1_SS_SS1 ((uint32_t)0x2UL) |
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#define | MXC_S_SPIXR_CTRL1_SS_SS1 (MXC_V_SPIXR_CTRL1_SS_SS1 << MXC_F_SPIXR_CTRL1_SS_POS) |
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#define | MXC_V_SPIXR_CTRL1_SS_SS2 ((uint32_t)0x4UL) |
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#define | MXC_S_SPIXR_CTRL1_SS_SS2 (MXC_V_SPIXR_CTRL1_SS_SS2 << MXC_F_SPIXR_CTRL1_SS_POS) |
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#define | MXC_V_SPIXR_CTRL1_SS_SS3 ((uint32_t)0x8UL) |
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#define | MXC_S_SPIXR_CTRL1_SS_SS3 (MXC_V_SPIXR_CTRL1_SS_SS3 << MXC_F_SPIXR_CTRL1_SS_POS) |
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#define | MXC_V_SPIXR_CTRL1_SS_SS4 ((uint32_t)0x10UL) |
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#define | MXC_S_SPIXR_CTRL1_SS_SS4 (MXC_V_SPIXR_CTRL1_SS_SS4 << MXC_F_SPIXR_CTRL1_SS_POS) |
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#define | MXC_V_SPIXR_CTRL1_SS_SS5 ((uint32_t)0x20UL) |
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#define | MXC_S_SPIXR_CTRL1_SS_SS5 (MXC_V_SPIXR_CTRL1_SS_SS5 << MXC_F_SPIXR_CTRL1_SS_POS) |
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#define | MXC_V_SPIXR_CTRL1_SS_SS6 ((uint32_t)0x40UL) |
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#define | MXC_S_SPIXR_CTRL1_SS_SS6 (MXC_V_SPIXR_CTRL1_SS_SS6 << MXC_F_SPIXR_CTRL1_SS_POS) |
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#define | MXC_V_SPIXR_CTRL1_SS_SS7 ((uint32_t)0x80UL) |
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#define | MXC_S_SPIXR_CTRL1_SS_SS7 (MXC_V_SPIXR_CTRL1_SS_SS7 << MXC_F_SPIXR_CTRL1_SS_POS) |
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#define | MXC_F_SPIXR_CTRL2_TX_NUM_CHAR_POS 0 |
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#define | MXC_F_SPIXR_CTRL2_TX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPIXR_CTRL2_TX_NUM_CHAR_POS)) |
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#define | MXC_F_SPIXR_CTRL2_RX_NUM_CHAR_POS 16 |
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#define | MXC_F_SPIXR_CTRL2_RX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPIXR_CTRL2_RX_NUM_CHAR_POS)) |
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#define | MXC_F_SPIXR_CTRL3_CPHA_POS 0 |
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#define | MXC_F_SPIXR_CTRL3_CPHA ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL3_CPHA_POS)) |
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#define | MXC_F_SPIXR_CTRL3_CPOL_POS 1 |
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#define | MXC_F_SPIXR_CTRL3_CPOL ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL3_CPOL_POS)) |
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#define | MXC_F_SPIXR_CTRL3_SCLK_FB_INV_POS 4 |
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#define | MXC_F_SPIXR_CTRL3_SCLK_FB_INV ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL3_SCLK_FB_INV_POS)) |
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#define | MXC_F_SPIXR_CTRL3_NUMBITS_POS 8 |
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#define | MXC_F_SPIXR_CTRL3_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPIXR_CTRL3_NUMBITS_POS)) |
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#define | MXC_V_SPIXR_CTRL3_NUMBITS_0 ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_CTRL3_NUMBITS_0 (MXC_V_SPIXR_CTRL3_NUMBITS_0 << MXC_F_SPIXR_CTRL3_NUMBITS_POS) |
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#define | MXC_F_SPIXR_CTRL3_DATA_WIDTH_POS 12 |
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#define | MXC_F_SPIXR_CTRL3_DATA_WIDTH ((uint32_t)(0x3UL << MXC_F_SPIXR_CTRL3_DATA_WIDTH_POS)) |
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#define | MXC_V_SPIXR_CTRL3_DATA_WIDTH_MONO ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_CTRL3_DATA_WIDTH_MONO (MXC_V_SPIXR_CTRL3_DATA_WIDTH_MONO << MXC_F_SPIXR_CTRL3_DATA_WIDTH_POS) |
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#define | MXC_V_SPIXR_CTRL3_DATA_WIDTH_DUAL ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_CTRL3_DATA_WIDTH_DUAL (MXC_V_SPIXR_CTRL3_DATA_WIDTH_DUAL << MXC_F_SPIXR_CTRL3_DATA_WIDTH_POS) |
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#define | MXC_V_SPIXR_CTRL3_DATA_WIDTH_QUAD ((uint32_t)0x2UL) |
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#define | MXC_S_SPIXR_CTRL3_DATA_WIDTH_QUAD (MXC_V_SPIXR_CTRL3_DATA_WIDTH_QUAD << MXC_F_SPIXR_CTRL3_DATA_WIDTH_POS) |
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#define | MXC_F_SPIXR_CTRL3_THREE_WIRE_POS 15 |
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#define | MXC_F_SPIXR_CTRL3_THREE_WIRE ((uint32_t)(0x1UL << MXC_F_SPIXR_CTRL3_THREE_WIRE_POS)) |
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#define | MXC_F_SPIXR_CTRL3_SSPOL_POS 16 |
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#define | MXC_F_SPIXR_CTRL3_SSPOL ((uint32_t)(0xFFUL << MXC_F_SPIXR_CTRL3_SSPOL_POS)) |
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#define | MXC_V_SPIXR_CTRL3_SSPOL_SS0_HIGH ((uint32_t)0x1UL) |
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#define | MXC_S_SPIXR_CTRL3_SSPOL_SS0_HIGH (MXC_V_SPIXR_CTRL3_SSPOL_SS0_HIGH << MXC_F_SPIXR_CTRL3_SSPOL_POS) |
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#define | MXC_V_SPIXR_CTRL3_SSPOL_SS1_HIGH ((uint32_t)0x2UL) |
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#define | MXC_S_SPIXR_CTRL3_SSPOL_SS1_HIGH (MXC_V_SPIXR_CTRL3_SSPOL_SS1_HIGH << MXC_F_SPIXR_CTRL3_SSPOL_POS) |
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#define | MXC_V_SPIXR_CTRL3_SSPOL_SS2_HIGH ((uint32_t)0x4UL) |
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#define | MXC_S_SPIXR_CTRL3_SSPOL_SS2_HIGH (MXC_V_SPIXR_CTRL3_SSPOL_SS2_HIGH << MXC_F_SPIXR_CTRL3_SSPOL_POS) |
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#define | MXC_V_SPIXR_CTRL3_SSPOL_SS3_HIGH ((uint32_t)0x8UL) |
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#define | MXC_S_SPIXR_CTRL3_SSPOL_SS3_HIGH (MXC_V_SPIXR_CTRL3_SSPOL_SS3_HIGH << MXC_F_SPIXR_CTRL3_SSPOL_POS) |
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#define | MXC_V_SPIXR_CTRL3_SSPOL_SS4_HIGH ((uint32_t)0x10UL) |
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#define | MXC_S_SPIXR_CTRL3_SSPOL_SS4_HIGH (MXC_V_SPIXR_CTRL3_SSPOL_SS4_HIGH << MXC_F_SPIXR_CTRL3_SSPOL_POS) |
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#define | MXC_V_SPIXR_CTRL3_SSPOL_SS5_HIGH ((uint32_t)0x20UL) |
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#define | MXC_S_SPIXR_CTRL3_SSPOL_SS5_HIGH (MXC_V_SPIXR_CTRL3_SSPOL_SS5_HIGH << MXC_F_SPIXR_CTRL3_SSPOL_POS) |
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#define | MXC_V_SPIXR_CTRL3_SSPOL_SS6_HIGH ((uint32_t)0x40UL) |
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#define | MXC_S_SPIXR_CTRL3_SSPOL_SS6_HIGH (MXC_V_SPIXR_CTRL3_SSPOL_SS6_HIGH << MXC_F_SPIXR_CTRL3_SSPOL_POS) |
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#define | MXC_V_SPIXR_CTRL3_SSPOL_SS7_HIGH ((uint32_t)0x80UL) |
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#define | MXC_S_SPIXR_CTRL3_SSPOL_SS7_HIGH (MXC_V_SPIXR_CTRL3_SSPOL_SS7_HIGH << MXC_F_SPIXR_CTRL3_SSPOL_POS) |
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#define | MXC_F_SPIXR_CTRL4_SSACT1_POS 0 |
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#define | MXC_F_SPIXR_CTRL4_SSACT1 ((uint32_t)(0xFFUL << MXC_F_SPIXR_CTRL4_SSACT1_POS)) |
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#define | MXC_V_SPIXR_CTRL4_SSACT1_256 ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_CTRL4_SSACT1_256 (MXC_V_SPIXR_CTRL4_SSACT1_256 << MXC_F_SPIXR_CTRL4_SSACT1_POS) |
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#define | MXC_F_SPIXR_CTRL4_SSACT2_POS 8 |
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#define | MXC_F_SPIXR_CTRL4_SSACT2 ((uint32_t)(0xFFUL << MXC_F_SPIXR_CTRL4_SSACT2_POS)) |
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#define | MXC_V_SPIXR_CTRL4_SSACT2_256 ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_CTRL4_SSACT2_256 (MXC_V_SPIXR_CTRL4_SSACT2_256 << MXC_F_SPIXR_CTRL4_SSACT2_POS) |
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#define | MXC_F_SPIXR_CTRL4_SSINACT_POS 16 |
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#define | MXC_F_SPIXR_CTRL4_SSINACT ((uint32_t)(0xFFUL << MXC_F_SPIXR_CTRL4_SSINACT_POS)) |
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#define | MXC_V_SPIXR_CTRL4_SSINACT_256 ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_CTRL4_SSINACT_256 (MXC_V_SPIXR_CTRL4_SSINACT_256 << MXC_F_SPIXR_CTRL4_SSINACT_POS) |
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#define | MXC_F_SPIXR_BRG_CTRL_LOW_POS 0 |
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#define | MXC_F_SPIXR_BRG_CTRL_LOW ((uint32_t)(0xFFUL << MXC_F_SPIXR_BRG_CTRL_LOW_POS)) |
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#define | MXC_V_SPIXR_BRG_CTRL_LOW_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_BRG_CTRL_LOW_DIS (MXC_V_SPIXR_BRG_CTRL_LOW_DIS << MXC_F_SPIXR_BRG_CTRL_LOW_POS) |
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#define | MXC_F_SPIXR_BRG_CTRL_HI_POS 8 |
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#define | MXC_F_SPIXR_BRG_CTRL_HI ((uint32_t)(0xFFUL << MXC_F_SPIXR_BRG_CTRL_HI_POS)) |
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#define | MXC_V_SPIXR_BRG_CTRL_HI_DIS ((uint32_t)0x0UL) |
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#define | MXC_S_SPIXR_BRG_CTRL_HI_DIS (MXC_V_SPIXR_BRG_CTRL_HI_DIS << MXC_F_SPIXR_BRG_CTRL_HI_POS) |
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#define | MXC_F_SPIXR_BRG_CTRL_SCALE_POS 16 |
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#define | MXC_F_SPIXR_BRG_CTRL_SCALE ((uint32_t)(0xFUL << MXC_F_SPIXR_BRG_CTRL_SCALE_POS)) |
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#define | MXC_F_SPIXR_DMA_TX_FIFO_LEVEL_POS 0 |
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#define | MXC_F_SPIXR_DMA_TX_FIFO_LEVEL ((uint32_t)(0x3FUL << MXC_F_SPIXR_DMA_TX_FIFO_LEVEL_POS)) |
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#define | MXC_F_SPIXR_DMA_TX_FIFO_EN_POS 6 |
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#define | MXC_F_SPIXR_DMA_TX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_TX_FIFO_EN_POS)) |
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#define | MXC_F_SPIXR_DMA_TX_FIFO_CLEAR_POS 7 |
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#define | MXC_F_SPIXR_DMA_TX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_TX_FIFO_CLEAR_POS)) |
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#define | MXC_F_SPIXR_DMA_TX_FIFO_CNT_POS 8 |
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#define | MXC_F_SPIXR_DMA_TX_FIFO_CNT ((uint32_t)(0x1FUL << MXC_F_SPIXR_DMA_TX_FIFO_CNT_POS)) |
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#define | MXC_F_SPIXR_DMA_TX_DMA_EN_POS 15 |
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#define | MXC_F_SPIXR_DMA_TX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_TX_DMA_EN_POS)) |
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#define | MXC_F_SPIXR_DMA_RX_FIFO_LEVEL_POS 16 |
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#define | MXC_F_SPIXR_DMA_RX_FIFO_LEVEL ((uint32_t)(0x3FUL << MXC_F_SPIXR_DMA_RX_FIFO_LEVEL_POS)) |
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#define | MXC_F_SPIXR_DMA_RX_FIFO_EN_POS 22 |
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#define | MXC_F_SPIXR_DMA_RX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_RX_FIFO_EN_POS)) |
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#define | MXC_F_SPIXR_DMA_RX_FIFO_CLEAR_POS 23 |
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#define | MXC_F_SPIXR_DMA_RX_FIFO_CLEAR ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_RX_FIFO_CLEAR_POS)) |
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#define | MXC_F_SPIXR_DMA_RX_FIFO_CNT_POS 24 |
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#define | MXC_F_SPIXR_DMA_RX_FIFO_CNT ((uint32_t)(0x3FUL << MXC_F_SPIXR_DMA_RX_FIFO_CNT_POS)) |
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#define | MXC_F_SPIXR_DMA_RX_DMA_EN_POS 31 |
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#define | MXC_F_SPIXR_DMA_RX_DMA_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_DMA_RX_DMA_EN_POS)) |
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#define | MXC_F_SPIXR_IRQ_TX_THRESH_POS 0 |
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#define | MXC_F_SPIXR_IRQ_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_TX_THRESH_POS)) |
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#define | MXC_F_SPIXR_IRQ_TX_EMPTY_POS 1 |
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#define | MXC_F_SPIXR_IRQ_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_TX_EMPTY_POS)) |
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#define | MXC_F_SPIXR_IRQ_RX_THRESH_POS 2 |
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#define | MXC_F_SPIXR_IRQ_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_RX_THRESH_POS)) |
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#define | MXC_F_SPIXR_IRQ_RX_FULL_POS 3 |
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#define | MXC_F_SPIXR_IRQ_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_RX_FULL_POS)) |
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#define | MXC_F_SPIXR_IRQ_SSA_POS 4 |
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#define | MXC_F_SPIXR_IRQ_SSA ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_SSA_POS)) |
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#define | MXC_F_SPIXR_IRQ_SSD_POS 5 |
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#define | MXC_F_SPIXR_IRQ_SSD ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_SSD_POS)) |
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#define | MXC_F_SPIXR_IRQ_FAULT_POS 8 |
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#define | MXC_F_SPIXR_IRQ_FAULT ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_FAULT_POS)) |
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#define | MXC_F_SPIXR_IRQ_ABORT_POS 9 |
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#define | MXC_F_SPIXR_IRQ_ABORT ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_ABORT_POS)) |
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#define | MXC_F_SPIXR_IRQ_M_DONE_POS 11 |
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#define | MXC_F_SPIXR_IRQ_M_DONE ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_M_DONE_POS)) |
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#define | MXC_F_SPIXR_IRQ_TX_OVR_POS 12 |
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#define | MXC_F_SPIXR_IRQ_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_TX_OVR_POS)) |
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#define | MXC_F_SPIXR_IRQ_TX_UND_POS 13 |
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#define | MXC_F_SPIXR_IRQ_TX_UND ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_TX_UND_POS)) |
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#define | MXC_F_SPIXR_IRQ_RX_OVR_POS 14 |
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#define | MXC_F_SPIXR_IRQ_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_RX_OVR_POS)) |
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#define | MXC_F_SPIXR_IRQ_RX_UND_POS 15 |
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#define | MXC_F_SPIXR_IRQ_RX_UND ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQ_RX_UND_POS)) |
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#define | MXC_F_SPIXR_IRQE_TX_THRESH_POS 0 |
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#define | MXC_F_SPIXR_IRQE_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_TX_THRESH_POS)) |
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#define | MXC_F_SPIXR_IRQE_TX_EMPTY_POS 1 |
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#define | MXC_F_SPIXR_IRQE_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_TX_EMPTY_POS)) |
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#define | MXC_F_SPIXR_IRQE_RX_THRESH_POS 2 |
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#define | MXC_F_SPIXR_IRQE_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_RX_THRESH_POS)) |
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#define | MXC_F_SPIXR_IRQE_RX_FULL_POS 3 |
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#define | MXC_F_SPIXR_IRQE_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_RX_FULL_POS)) |
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#define | MXC_F_SPIXR_IRQE_SSA_POS 4 |
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#define | MXC_F_SPIXR_IRQE_SSA ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_SSA_POS)) |
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#define | MXC_F_SPIXR_IRQE_SSD_POS 5 |
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#define | MXC_F_SPIXR_IRQE_SSD ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_SSD_POS)) |
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#define | MXC_F_SPIXR_IRQE_FAULT_POS 8 |
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#define | MXC_F_SPIXR_IRQE_FAULT ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_FAULT_POS)) |
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#define | MXC_F_SPIXR_IRQE_ABORT_POS 9 |
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#define | MXC_F_SPIXR_IRQE_ABORT ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_ABORT_POS)) |
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#define | MXC_F_SPIXR_IRQE_M_DONE_POS 11 |
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#define | MXC_F_SPIXR_IRQE_M_DONE ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_M_DONE_POS)) |
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#define | MXC_F_SPIXR_IRQE_TX_OVR_POS 12 |
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#define | MXC_F_SPIXR_IRQE_TX_OVR ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_TX_OVR_POS)) |
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#define | MXC_F_SPIXR_IRQE_TX_UND_POS 13 |
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#define | MXC_F_SPIXR_IRQE_TX_UND ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_TX_UND_POS)) |
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#define | MXC_F_SPIXR_IRQE_RX_OVR_POS 14 |
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#define | MXC_F_SPIXR_IRQE_RX_OVR ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_RX_OVR_POS)) |
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#define | MXC_F_SPIXR_IRQE_RX_UND_POS 15 |
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#define | MXC_F_SPIXR_IRQE_RX_UND ((uint32_t)(0x1UL << MXC_F_SPIXR_IRQE_RX_UND_POS)) |
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#define | MXC_F_SPIXR_WAKE_TX_THRESH_POS 0 |
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#define | MXC_F_SPIXR_WAKE_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKE_TX_THRESH_POS)) |
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#define | MXC_F_SPIXR_WAKE_TX_EMPTY_POS 1 |
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#define | MXC_F_SPIXR_WAKE_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKE_TX_EMPTY_POS)) |
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#define | MXC_F_SPIXR_WAKE_RX_THRESH_POS 2 |
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#define | MXC_F_SPIXR_WAKE_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKE_RX_THRESH_POS)) |
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#define | MXC_F_SPIXR_WAKE_RX_FULL_POS 3 |
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#define | MXC_F_SPIXR_WAKE_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKE_RX_FULL_POS)) |
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#define | MXC_F_SPIXR_WAKEE_TX_THRESH_POS 0 |
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#define | MXC_F_SPIXR_WAKEE_TX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKEE_TX_THRESH_POS)) |
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#define | MXC_F_SPIXR_WAKEE_TX_EMPTY_POS 1 |
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#define | MXC_F_SPIXR_WAKEE_TX_EMPTY ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKEE_TX_EMPTY_POS)) |
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#define | MXC_F_SPIXR_WAKEE_RX_THRESH_POS 2 |
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#define | MXC_F_SPIXR_WAKEE_RX_THRESH ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKEE_RX_THRESH_POS)) |
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#define | MXC_F_SPIXR_WAKEE_RX_FULL_POS 3 |
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#define | MXC_F_SPIXR_WAKEE_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPIXR_WAKEE_RX_FULL_POS)) |
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#define | MXC_F_SPIXR_STAT_BUSY_POS 0 |
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#define | MXC_F_SPIXR_STAT_BUSY ((uint32_t)(0x1UL << MXC_F_SPIXR_STAT_BUSY_POS)) |
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#define | MXC_F_SPIXR_XMEM_CTRL_RD_CMD_POS 0 |
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#define | MXC_F_SPIXR_XMEM_CTRL_RD_CMD ((uint32_t)(0xFFUL << MXC_F_SPIXR_XMEM_CTRL_RD_CMD_POS)) |
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#define | MXC_F_SPIXR_XMEM_CTRL_WR_CMD_POS 8 |
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#define | MXC_F_SPIXR_XMEM_CTRL_WR_CMD ((uint32_t)(0xFFUL << MXC_F_SPIXR_XMEM_CTRL_WR_CMD_POS)) |
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#define | MXC_F_SPIXR_XMEM_CTRL_DUMMY_CLK_POS 16 |
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#define | MXC_F_SPIXR_XMEM_CTRL_DUMMY_CLK ((uint32_t)(0xFFUL << MXC_F_SPIXR_XMEM_CTRL_DUMMY_CLK_POS)) |
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#define | MXC_F_SPIXR_XMEM_CTRL_XMEM_EN_POS 31 |
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#define | MXC_F_SPIXR_XMEM_CTRL_XMEM_EN ((uint32_t)(0x1UL << MXC_F_SPIXR_XMEM_CTRL_XMEM_EN_POS)) |
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