srcc_regs.h

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/******************************************************************************
 *
 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 
 * Analog Devices, Inc.),
 * Copyright (C) 2023-2024 Analog Devices, Inc.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 ******************************************************************************/
 
#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_SRCC_REGS_H_
#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_SRCC_REGS_H_
 
/* **** Includes **** */
#include <stdint.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
#if defined (__ICCARM__)
  #pragma system_include
#endif
 
#if defined (__CC_ARM)
  #pragma anon_unions
#endif
/*
    If types are not defined elsewhere (CMSIS) define them here
*/
#ifndef __IO
#define __IO volatile
#endif
#ifndef __I
#define __I  volatile const
#endif
#ifndef __O
#define __O  volatile
#endif
#ifndef __R
#define __R  volatile const
#endif
 
/* **** Definitions **** */
 
typedef struct {
    __I  uint32_t cache_id;             
    __I  uint32_t memcfg;               
    __R  uint32_t rsv_0x8_0xff[62];
    __IO uint32_t cache_ctrl;           
    __R  uint32_t rsv_0x104_0x6ff[383];
    __IO uint32_t invalidate;           
} mxc_srcc_regs_t;
 
/* Register offsets for module SRCC */
#define MXC_R_SRCC_CACHE_ID                ((uint32_t)0x00000000UL) 
#define MXC_R_SRCC_MEMCFG                  ((uint32_t)0x00000004UL) 
#define MXC_R_SRCC_CACHE_CTRL              ((uint32_t)0x00000100UL) 
#define MXC_R_SRCC_INVALIDATE              ((uint32_t)0x00000700UL) 
#define MXC_F_SRCC_CACHE_ID_RELNUM_POS                 0 
#define MXC_F_SRCC_CACHE_ID_RELNUM                     ((uint32_t)(0x3FUL << MXC_F_SRCC_CACHE_ID_RELNUM_POS)) 
#define MXC_F_SRCC_CACHE_ID_PARTNUM_POS                6 
#define MXC_F_SRCC_CACHE_ID_PARTNUM                    ((uint32_t)(0xFUL << MXC_F_SRCC_CACHE_ID_PARTNUM_POS)) 
#define MXC_F_SRCC_CACHE_ID_CCHID_POS                  10 
#define MXC_F_SRCC_CACHE_ID_CCHID                      ((uint32_t)(0x3FUL << MXC_F_SRCC_CACHE_ID_CCHID_POS)) 
#define MXC_F_SRCC_MEMCFG_CCHSZ_POS                    0 
#define MXC_F_SRCC_MEMCFG_CCHSZ                        ((uint32_t)(0xFFFFUL << MXC_F_SRCC_MEMCFG_CCHSZ_POS)) 
#define MXC_F_SRCC_MEMCFG_MEMSZ_POS                    16 
#define MXC_F_SRCC_MEMCFG_MEMSZ                        ((uint32_t)(0xFFFFUL << MXC_F_SRCC_MEMCFG_MEMSZ_POS)) 
#define MXC_F_SRCC_CACHE_CTRL_CACHE_EN_POS             0 
#define MXC_F_SRCC_CACHE_CTRL_CACHE_EN                 ((uint32_t)(0x1UL << MXC_F_SRCC_CACHE_CTRL_CACHE_EN_POS)) 
#define MXC_F_SRCC_CACHE_CTRL_WRITE_ALLOC_POS          1 
#define MXC_F_SRCC_CACHE_CTRL_WRITE_ALLOC              ((uint32_t)(0x1UL << MXC_F_SRCC_CACHE_CTRL_WRITE_ALLOC_POS)) 
#define MXC_F_SRCC_CACHE_CTRL_CWFST_DIS_POS            2 
#define MXC_F_SRCC_CACHE_CTRL_CWFST_DIS                ((uint32_t)(0x1UL << MXC_F_SRCC_CACHE_CTRL_CWFST_DIS_POS)) 
#define MXC_F_SRCC_CACHE_CTRL_CACHE_RDY_POS            16 
#define MXC_F_SRCC_CACHE_CTRL_CACHE_RDY                ((uint32_t)(0x1UL << MXC_F_SRCC_CACHE_CTRL_CACHE_RDY_POS)) 
#define MXC_F_SRCC_INVALIDATE_IA_POS                   0 
#define MXC_F_SRCC_INVALIDATE_IA                       ((uint32_t)(0xFFFFFFFFUL << MXC_F_SRCC_INVALIDATE_IA_POS)) 
#ifdef __cplusplus
}
#endif
 
#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_SRCC_REGS_H_