ADC_CHSEL3

Macros
#define	MXC_F_ADC_CHSEL3_SLOT12_ID_POS   0
#define	MXC_F_ADC_CHSEL3_SLOT12_ID   ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL3_SLOT12_ID_POS))
#define	MXC_F_ADC_CHSEL3_SLOT13_ID_POS   8
#define	MXC_F_ADC_CHSEL3_SLOT13_ID   ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL3_SLOT13_ID_POS))
#define	MXC_F_ADC_CHSEL3_SLOT14_ID_POS   16
#define	MXC_F_ADC_CHSEL3_SLOT14_ID   ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL3_SLOT14_ID_POS))
#define	MXC_F_ADC_CHSEL3_SLOT15_ID_POS   24
#define	MXC_F_ADC_CHSEL3_SLOT15_ID   ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL3_SLOT15_ID_POS))

Detailed Description

Channel Select Register 3.

Macro Definition Documentation

MXC_F_ADC_CHSEL3_SLOT12_ID

#define MXC_F_ADC_CHSEL3_SLOT12_ID   ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL3_SLOT12_ID_POS))

CHSEL3_SLOT12_ID Mask

MXC_F_ADC_CHSEL3_SLOT12_ID_POS

#define MXC_F_ADC_CHSEL3_SLOT12_ID_POS   0

CHSEL3_SLOT12_ID Position

MXC_F_ADC_CHSEL3_SLOT13_ID

#define MXC_F_ADC_CHSEL3_SLOT13_ID   ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL3_SLOT13_ID_POS))

CHSEL3_SLOT13_ID Mask

MXC_F_ADC_CHSEL3_SLOT13_ID_POS

#define MXC_F_ADC_CHSEL3_SLOT13_ID_POS   8

CHSEL3_SLOT13_ID Position

MXC_F_ADC_CHSEL3_SLOT14_ID

#define MXC_F_ADC_CHSEL3_SLOT14_ID   ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL3_SLOT14_ID_POS))

CHSEL3_SLOT14_ID Mask

MXC_F_ADC_CHSEL3_SLOT14_ID_POS

#define MXC_F_ADC_CHSEL3_SLOT14_ID_POS   16

CHSEL3_SLOT14_ID Position

MXC_F_ADC_CHSEL3_SLOT15_ID

#define MXC_F_ADC_CHSEL3_SLOT15_ID   ((uint32_t)(0x1FUL << MXC_F_ADC_CHSEL3_SLOT15_ID_POS))

CHSEL3_SLOT15_ID Mask

MXC_F_ADC_CHSEL3_SLOT15_ID_POS

#define MXC_F_ADC_CHSEL3_SLOT15_ID_POS   24

CHSEL3_SLOT15_ID Position