Macros
#define	MXC_R_CTB_CTRL ((uint32_t)0x00000000UL)

#define	MXC_R_CTB_CIPHER_CTRL ((uint32_t)0x00000004UL)

#define	MXC_R_CTB_HASH_CTRL ((uint32_t)0x00000008UL)

#define	MXC_R_CTB_CRC_CTRL ((uint32_t)0x0000000CUL)

#define	MXC_R_CTB_DMA_SRC ((uint32_t)0x00000010UL)

#define	MXC_R_CTB_DMA_DEST ((uint32_t)0x00000014UL)

#define	MXC_R_CTB_DMA_CNT ((uint32_t)0x00000018UL)

#define	MXC_R_CTB_DIN ((uint32_t)0x00000020UL)

#define	MXC_R_CTB_DOUT ((uint32_t)0x00000030UL)

#define	MXC_R_CTB_CRC_POLY ((uint32_t)0x00000040UL)

#define	MXC_R_CTB_CRC_VAL ((uint32_t)0x00000044UL)

#define	MXC_R_CTB_HAM_ECC ((uint32_t)0x0000004CUL)

#define	MXC_R_CTB_CIPHER_INIT ((uint32_t)0x00000050UL)

#define	MXC_R_CTB_CIPHER_KEY ((uint32_t)0x00000060UL)

#define	MXC_R_CTB_HASH_DIGEST ((uint32_t)0x00000080UL)

#define	MXC_R_CTB_HASH_MSG_SZ ((uint32_t)0x000000C0UL)

#define	MXC_R_CTB_AAD_LENGTH ((uint32_t)0x000000D0UL)

#define	MXC_R_CTB_PLD_LENGTH ((uint32_t)0x000000D8UL)

#define	MXC_R_CTB_TAGMIC ((uint32_t)0x000000E0UL)

#define	MXC_R_CTB_SCA_CTRL0 ((uint32_t)0x00000100UL)

#define	MXC_R_CTB_SCA_CTRL1 ((uint32_t)0x00000104UL)

#define	MXC_R_CTB_SCA_STAT ((uint32_t)0x00000108UL)

#define	MXC_R_CTB_SCA_PPX_ADDR ((uint32_t)0x0000010CUL)

#define	MXC_R_CTB_SCA_PPY_ADDR ((uint32_t)0x00000110UL)

#define	MXC_R_CTB_SCA_PPZ_ADDR ((uint32_t)0x00000114UL)

#define	MXC_R_CTB_SCA_PQX_ADDR ((uint32_t)0x00000118UL)

#define	MXC_R_CTB_SCA_PQY_ADDR ((uint32_t)0x0000011CUL)

#define	MXC_R_CTB_SCA_PQZ_ADDR ((uint32_t)0x00000120UL)

#define	MXC_R_CTB_SCA_RDSA_ADDR ((uint32_t)0x00000124UL)

#define	MXC_R_CTB_SCA_RES_ADDR ((uint32_t)0x00000128UL)

#define	MXC_R_CTB_SCA_OP_BUFF_ADDR ((uint32_t)0x0000012CUL)

#define	MXC_R_CTB_SCA_MODDATA ((uint32_t)0x00000130UL)

#define	MXC_R_CTB_SCA_NRNG ((uint32_t)0x00000134UL)

Detailed Description

CTB Peripheral Register Offsets from the CTB Base Peripheral Address.

Macro Definition Documentation

◆ MXC_R_CTB_AAD_LENGTH

#define MXC_R_CTB_AAD_LENGTH ((uint32_t)0x000000D0UL)

Offset from CTB Base Address: 0x00D0

◆ MXC_R_CTB_CIPHER_CTRL

#define MXC_R_CTB_CIPHER_CTRL ((uint32_t)0x00000004UL)

Offset from CTB Base Address: 0x0004

◆ MXC_R_CTB_CIPHER_INIT

#define MXC_R_CTB_CIPHER_INIT ((uint32_t)0x00000050UL)

Offset from CTB Base Address: 0x0050

◆ MXC_R_CTB_CIPHER_KEY

#define MXC_R_CTB_CIPHER_KEY ((uint32_t)0x00000060UL)

Offset from CTB Base Address: 0x0060

◆ MXC_R_CTB_CRC_CTRL

#define MXC_R_CTB_CRC_CTRL ((uint32_t)0x0000000CUL)

Offset from CTB Base Address: 0x000C

◆ MXC_R_CTB_CRC_POLY

#define MXC_R_CTB_CRC_POLY ((uint32_t)0x00000040UL)

Offset from CTB Base Address: 0x0040

◆ MXC_R_CTB_CRC_VAL

#define MXC_R_CTB_CRC_VAL ((uint32_t)0x00000044UL)

Offset from CTB Base Address: 0x0044

◆ MXC_R_CTB_CTRL

#define MXC_R_CTB_CTRL ((uint32_t)0x00000000UL)

Offset from CTB Base Address: 0x0000

◆ MXC_R_CTB_DIN

#define MXC_R_CTB_DIN ((uint32_t)0x00000020UL)

Offset from CTB Base Address: 0x0020

◆ MXC_R_CTB_DMA_CNT

#define MXC_R_CTB_DMA_CNT ((uint32_t)0x00000018UL)

Offset from CTB Base Address: 0x0018

◆ MXC_R_CTB_DMA_DEST

#define MXC_R_CTB_DMA_DEST ((uint32_t)0x00000014UL)

Offset from CTB Base Address: 0x0014

◆ MXC_R_CTB_DMA_SRC

#define MXC_R_CTB_DMA_SRC ((uint32_t)0x00000010UL)

Offset from CTB Base Address: 0x0010

◆ MXC_R_CTB_DOUT

#define MXC_R_CTB_DOUT ((uint32_t)0x00000030UL)

Offset from CTB Base Address: 0x0030

◆ MXC_R_CTB_HAM_ECC

#define MXC_R_CTB_HAM_ECC ((uint32_t)0x0000004CUL)

Offset from CTB Base Address: 0x004C

◆ MXC_R_CTB_HASH_CTRL

#define MXC_R_CTB_HASH_CTRL ((uint32_t)0x00000008UL)

Offset from CTB Base Address: 0x0008

◆ MXC_R_CTB_HASH_DIGEST

#define MXC_R_CTB_HASH_DIGEST ((uint32_t)0x00000080UL)

Offset from CTB Base Address: 0x0080

◆ MXC_R_CTB_HASH_MSG_SZ

#define MXC_R_CTB_HASH_MSG_SZ ((uint32_t)0x000000C0UL)

Offset from CTB Base Address: 0x00C0

◆ MXC_R_CTB_PLD_LENGTH

#define MXC_R_CTB_PLD_LENGTH ((uint32_t)0x000000D8UL)

Offset from CTB Base Address: 0x00D8

◆ MXC_R_CTB_SCA_CTRL0

#define MXC_R_CTB_SCA_CTRL0 ((uint32_t)0x00000100UL)

Offset from CTB Base Address: 0x0100

◆ MXC_R_CTB_SCA_CTRL1

#define MXC_R_CTB_SCA_CTRL1 ((uint32_t)0x00000104UL)

Offset from CTB Base Address: 0x0104

◆ MXC_R_CTB_SCA_MODDATA

#define MXC_R_CTB_SCA_MODDATA ((uint32_t)0x00000130UL)

Offset from CTB Base Address: 0x0130

◆ MXC_R_CTB_SCA_NRNG

#define MXC_R_CTB_SCA_NRNG ((uint32_t)0x00000134UL)

Offset from CTB Base Address: 0x0134

◆ MXC_R_CTB_SCA_OP_BUFF_ADDR

#define MXC_R_CTB_SCA_OP_BUFF_ADDR ((uint32_t)0x0000012CUL)

Offset from CTB Base Address: 0x012C

◆ MXC_R_CTB_SCA_PPX_ADDR

#define MXC_R_CTB_SCA_PPX_ADDR ((uint32_t)0x0000010CUL)

Offset from CTB Base Address: 0x010C

◆ MXC_R_CTB_SCA_PPY_ADDR

#define MXC_R_CTB_SCA_PPY_ADDR ((uint32_t)0x00000110UL)

Offset from CTB Base Address: 0x0110

◆ MXC_R_CTB_SCA_PPZ_ADDR

#define MXC_R_CTB_SCA_PPZ_ADDR ((uint32_t)0x00000114UL)

Offset from CTB Base Address: 0x0114

◆ MXC_R_CTB_SCA_PQX_ADDR

#define MXC_R_CTB_SCA_PQX_ADDR ((uint32_t)0x00000118UL)

Offset from CTB Base Address: 0x0118

◆ MXC_R_CTB_SCA_PQY_ADDR

#define MXC_R_CTB_SCA_PQY_ADDR ((uint32_t)0x0000011CUL)

Offset from CTB Base Address: 0x011C

◆ MXC_R_CTB_SCA_PQZ_ADDR

#define MXC_R_CTB_SCA_PQZ_ADDR ((uint32_t)0x00000120UL)

Offset from CTB Base Address: 0x0120

◆ MXC_R_CTB_SCA_RDSA_ADDR

#define MXC_R_CTB_SCA_RDSA_ADDR ((uint32_t)0x00000124UL)

Offset from CTB Base Address: 0x0124

◆ MXC_R_CTB_SCA_RES_ADDR

#define MXC_R_CTB_SCA_RES_ADDR ((uint32_t)0x00000128UL)

Offset from CTB Base Address: 0x0128

◆ MXC_R_CTB_SCA_STAT

#define MXC_R_CTB_SCA_STAT ((uint32_t)0x00000108UL)

Offset from CTB Base Address: 0x0108

◆ MXC_R_CTB_TAGMIC

#define MXC_R_CTB_TAGMIC ((uint32_t)0x000000E0UL)

Offset from CTB Base Address: 0x00E0

Macros