DMA_INTFL

Macros
#define	MXC_F_DMA_INTFL_CH0_POS   0
#define	MXC_F_DMA_INTFL_CH0   ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH0_POS))
#define	MXC_F_DMA_INTFL_CH1_POS   1
#define	MXC_F_DMA_INTFL_CH1   ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH1_POS))
#define	MXC_F_DMA_INTFL_CH2_POS   2
#define	MXC_F_DMA_INTFL_CH2   ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH2_POS))
#define	MXC_F_DMA_INTFL_CH3_POS   3
#define	MXC_F_DMA_INTFL_CH3   ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH3_POS))
#define	MXC_F_DMA_INTFL_CH4_POS   4
#define	MXC_F_DMA_INTFL_CH4   ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH4_POS))
#define	MXC_F_DMA_INTFL_CH5_POS   5
#define	MXC_F_DMA_INTFL_CH5   ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH5_POS))
#define	MXC_F_DMA_INTFL_CH6_POS   6
#define	MXC_F_DMA_INTFL_CH6   ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH6_POS))
#define	MXC_F_DMA_INTFL_CH7_POS   7
#define	MXC_F_DMA_INTFL_CH7   ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH7_POS))

Detailed Description

DMA Interrupt Register.

Macro Definition Documentation

MXC_F_DMA_INTFL_CH0

#define MXC_F_DMA_INTFL_CH0   ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH0_POS))

INTFL_CH0 Mask

MXC_F_DMA_INTFL_CH0_POS

#define MXC_F_DMA_INTFL_CH0_POS   0

INTFL_CH0 Position

MXC_F_DMA_INTFL_CH1

#define MXC_F_DMA_INTFL_CH1   ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH1_POS))

INTFL_CH1 Mask

MXC_F_DMA_INTFL_CH1_POS

#define MXC_F_DMA_INTFL_CH1_POS   1

INTFL_CH1 Position

MXC_F_DMA_INTFL_CH2

#define MXC_F_DMA_INTFL_CH2   ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH2_POS))

INTFL_CH2 Mask

MXC_F_DMA_INTFL_CH2_POS

#define MXC_F_DMA_INTFL_CH2_POS   2

INTFL_CH2 Position

MXC_F_DMA_INTFL_CH3

#define MXC_F_DMA_INTFL_CH3   ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH3_POS))

INTFL_CH3 Mask

MXC_F_DMA_INTFL_CH3_POS

#define MXC_F_DMA_INTFL_CH3_POS   3

INTFL_CH3 Position

MXC_F_DMA_INTFL_CH4

#define MXC_F_DMA_INTFL_CH4   ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH4_POS))

INTFL_CH4 Mask

MXC_F_DMA_INTFL_CH4_POS

#define MXC_F_DMA_INTFL_CH4_POS   4

INTFL_CH4 Position

MXC_F_DMA_INTFL_CH5

#define MXC_F_DMA_INTFL_CH5   ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH5_POS))

INTFL_CH5 Mask

MXC_F_DMA_INTFL_CH5_POS

#define MXC_F_DMA_INTFL_CH5_POS   5

INTFL_CH5 Position

MXC_F_DMA_INTFL_CH6

#define MXC_F_DMA_INTFL_CH6   ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH6_POS))

INTFL_CH6 Mask

MXC_F_DMA_INTFL_CH6_POS

#define MXC_F_DMA_INTFL_CH6_POS   6

INTFL_CH6 Position

MXC_F_DMA_INTFL_CH7

#define MXC_F_DMA_INTFL_CH7   ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH7_POS))

INTFL_CH7 Mask

MXC_F_DMA_INTFL_CH7_POS

#define MXC_F_DMA_INTFL_CH7_POS   7

INTFL_CH7 Position