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MAX32672 Peripheral Driver API
Peripheral Driver API for the MAX32672
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Macros | |
| #define | MXC_F_GCR_RST1_I2C1_POS 0 |
| #define | MXC_F_GCR_RST1_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C1_POS)) |
| #define | MXC_F_GCR_RST1_WDT1_POS 8 |
| #define | MXC_F_GCR_RST1_WDT1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_WDT1_POS)) |
| #define | MXC_F_GCR_RST1_AES_POS 10 |
| #define | MXC_F_GCR_RST1_AES ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AES_POS)) |
| #define | MXC_F_GCR_RST1_AC_POS 14 |
| #define | MXC_F_GCR_RST1_AC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AC_POS)) |
| #define | MXC_F_GCR_RST1_I2C2_POS 17 |
| #define | MXC_F_GCR_RST1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C2_POS)) |
| #define | MXC_F_GCR_RST1_I2S_POS 23 |
| #define | MXC_F_GCR_RST1_I2S ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2S_POS)) |
| #define | MXC_F_GCR_RST1_QDEC_POS 25 |
| #define | MXC_F_GCR_RST1_QDEC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_QDEC_POS)) |
Reset 1.
| #define MXC_F_GCR_RST1_AC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AC_POS)) |
RST1_AC Mask
| #define MXC_F_GCR_RST1_AC_POS 14 |
RST1_AC Position
| #define MXC_F_GCR_RST1_AES ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AES_POS)) |
RST1_AES Mask
| #define MXC_F_GCR_RST1_AES_POS 10 |
RST1_AES Position
| #define MXC_F_GCR_RST1_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C1_POS)) |
RST1_I2C1 Mask
| #define MXC_F_GCR_RST1_I2C1_POS 0 |
RST1_I2C1 Position
| #define MXC_F_GCR_RST1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C2_POS)) |
RST1_I2C2 Mask
| #define MXC_F_GCR_RST1_I2C2_POS 17 |
RST1_I2C2 Position
| #define MXC_F_GCR_RST1_I2S ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2S_POS)) |
RST1_I2S Mask
| #define MXC_F_GCR_RST1_I2S_POS 23 |
RST1_I2S Position
| #define MXC_F_GCR_RST1_QDEC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_QDEC_POS)) |
RST1_QDEC Mask
| #define MXC_F_GCR_RST1_QDEC_POS 25 |
RST1_QDEC Position
| #define MXC_F_GCR_RST1_WDT1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_WDT1_POS)) |
RST1_WDT1 Mask
| #define MXC_F_GCR_RST1_WDT1_POS 8 |
RST1_WDT1 Position