I2C_INTEN1

Macros
#define	MXC_F_I2C_INTEN1_RX_OV_POS   0
#define	MXC_F_I2C_INTEN1_RX_OV   ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_RX_OV_POS))
#define	MXC_F_I2C_INTEN1_TX_UN_POS   1
#define	MXC_F_I2C_INTEN1_TX_UN   ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_TX_UN_POS))
#define	MXC_F_I2C_INTEN1_START_POS   2
#define	MXC_F_I2C_INTEN1_START   ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_START_POS))

Detailed Description

Interrupt Staus Register 1.

Macro Definition Documentation

MXC_F_I2C_INTEN1_RX_OV

#define MXC_F_I2C_INTEN1_RX_OV   ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_RX_OV_POS))

INTEN1_RX_OV Mask

MXC_F_I2C_INTEN1_RX_OV_POS

#define MXC_F_I2C_INTEN1_RX_OV_POS   0

INTEN1_RX_OV Position

MXC_F_I2C_INTEN1_START

#define MXC_F_I2C_INTEN1_START   ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_START_POS))

INTEN1_START Mask

MXC_F_I2C_INTEN1_START_POS

#define MXC_F_I2C_INTEN1_START_POS   2

INTEN1_START Position

MXC_F_I2C_INTEN1_TX_UN

#define MXC_F_I2C_INTEN1_TX_UN   ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_TX_UN_POS))

INTEN1_TX_UN Mask

MXC_F_I2C_INTEN1_TX_UN_POS

#define MXC_F_I2C_INTEN1_TX_UN_POS   1

INTEN1_TX_UN Position