Register Offsets

Macros
#define	MXC_R_MCR_RST   ((uint32_t)0x00000004UL)
#define	MXC_R_MCR_CLKCTRL   ((uint32_t)0x00000008UL)
#define	MXC_R_MCR_AINCOMP   ((uint32_t)0x0000000CUL)
#define	MXC_R_MCR_LPPIOCTRL   ((uint32_t)0x00000010UL)
#define	MXC_R_MCR_PCLKDIS   ((uint32_t)0x00000024UL)
#define	MXC_R_MCR_AESKEY   ((uint32_t)0x00000034UL)
#define	MXC_R_MCR_ADC_CFG0   ((uint32_t)0x00000038UL)
#define	MXC_R_MCR_ADC_CFG1   ((uint32_t)0x0000003CUL)
#define	MXC_R_MCR_ADC_CFG2   ((uint32_t)0x00000040UL)
#define	MXC_R_MCR_ADC_CFG3   ((uint32_t)0x00000044UL)

Detailed Description

MCR Peripheral Register Offsets from the MCR Base Peripheral Address.

Macro Definition Documentation

MXC_R_MCR_ADC_CFG0

#define MXC_R_MCR_ADC_CFG0   ((uint32_t)0x00000038UL)

Offset from MCR Base Address: 0x0038

MXC_R_MCR_ADC_CFG1

#define MXC_R_MCR_ADC_CFG1   ((uint32_t)0x0000003CUL)

Offset from MCR Base Address: 0x003C

MXC_R_MCR_ADC_CFG2

#define MXC_R_MCR_ADC_CFG2   ((uint32_t)0x00000040UL)

Offset from MCR Base Address: 0x0040

MXC_R_MCR_ADC_CFG3

#define MXC_R_MCR_ADC_CFG3   ((uint32_t)0x00000044UL)

Offset from MCR Base Address: 0x0044

MXC_R_MCR_AESKEY

#define MXC_R_MCR_AESKEY   ((uint32_t)0x00000034UL)

Offset from MCR Base Address: 0x0034

MXC_R_MCR_AINCOMP

#define MXC_R_MCR_AINCOMP   ((uint32_t)0x0000000CUL)

Offset from MCR Base Address: 0x000C

MXC_R_MCR_CLKCTRL

#define MXC_R_MCR_CLKCTRL   ((uint32_t)0x00000008UL)

Offset from MCR Base Address: 0x0008

MXC_R_MCR_LPPIOCTRL

#define MXC_R_MCR_LPPIOCTRL   ((uint32_t)0x00000010UL)

Offset from MCR Base Address: 0x0010

MXC_R_MCR_PCLKDIS

#define MXC_R_MCR_PCLKDIS   ((uint32_t)0x00000024UL)

Offset from MCR Base Address: 0x0024

MXC_R_MCR_RST

#define MXC_R_MCR_RST   ((uint32_t)0x00000004UL)

Offset from MCR Base Address: 0x0004