QDEC_CTRL

Macros
#define	MXC_F_QDEC_CTRL_EN_POS   0
#define	MXC_F_QDEC_CTRL_EN   ((uint32_t)(0x1UL << MXC_F_QDEC_CTRL_EN_POS))
#define	MXC_F_QDEC_CTRL_MODE_POS   1
#define	MXC_F_QDEC_CTRL_MODE   ((uint32_t)(0x3UL << MXC_F_QDEC_CTRL_MODE_POS))
#define	MXC_V_QDEC_CTRL_MODE_X1MODE   ((uint32_t)0x0UL)
#define	MXC_S_QDEC_CTRL_MODE_X1MODE   (MXC_V_QDEC_CTRL_MODE_X1MODE << MXC_F_QDEC_CTRL_MODE_POS)
#define	MXC_V_QDEC_CTRL_MODE_X2MODE   ((uint32_t)0x1UL)
#define	MXC_S_QDEC_CTRL_MODE_X2MODE   (MXC_V_QDEC_CTRL_MODE_X2MODE << MXC_F_QDEC_CTRL_MODE_POS)
#define	MXC_V_QDEC_CTRL_MODE_X4MODE   ((uint32_t)0x2UL)
#define	MXC_S_QDEC_CTRL_MODE_X4MODE   (MXC_V_QDEC_CTRL_MODE_X4MODE << MXC_F_QDEC_CTRL_MODE_POS)
#define	MXC_F_QDEC_CTRL_SWAP_POS   3
#define	MXC_F_QDEC_CTRL_SWAP   ((uint32_t)(0x1UL << MXC_F_QDEC_CTRL_SWAP_POS))
#define	MXC_F_QDEC_CTRL_FILTER_POS   4
#define	MXC_F_QDEC_CTRL_FILTER   ((uint32_t)(0x3UL << MXC_F_QDEC_CTRL_FILTER_POS))
#define	MXC_V_QDEC_CTRL_FILTER_1_SAMPLE   ((uint32_t)0x0UL)
#define	MXC_S_QDEC_CTRL_FILTER_1_SAMPLE   (MXC_V_QDEC_CTRL_FILTER_1_SAMPLE << MXC_F_QDEC_CTRL_FILTER_POS)
#define	MXC_V_QDEC_CTRL_FILTER_2_SAMPLES   ((uint32_t)0x1UL)
#define	MXC_S_QDEC_CTRL_FILTER_2_SAMPLES   (MXC_V_QDEC_CTRL_FILTER_2_SAMPLES << MXC_F_QDEC_CTRL_FILTER_POS)
#define	MXC_V_QDEC_CTRL_FILTER_3_SAMPLES   ((uint32_t)0x2UL)
#define	MXC_S_QDEC_CTRL_FILTER_3_SAMPLES   (MXC_V_QDEC_CTRL_FILTER_3_SAMPLES << MXC_F_QDEC_CTRL_FILTER_POS)
#define	MXC_V_QDEC_CTRL_FILTER_4_SAMPLES   ((uint32_t)0x3UL)
#define	MXC_S_QDEC_CTRL_FILTER_4_SAMPLES   (MXC_V_QDEC_CTRL_FILTER_4_SAMPLES << MXC_F_QDEC_CTRL_FILTER_POS)
#define	MXC_F_QDEC_CTRL_RST_INDEX_POS   6
#define	MXC_F_QDEC_CTRL_RST_INDEX   ((uint32_t)(0x1UL << MXC_F_QDEC_CTRL_RST_INDEX_POS))
#define	MXC_F_QDEC_CTRL_RST_MAXCNT_POS   7
#define	MXC_F_QDEC_CTRL_RST_MAXCNT   ((uint32_t)(0x1UL << MXC_F_QDEC_CTRL_RST_MAXCNT_POS))
#define	MXC_F_QDEC_CTRL_STICKY_POS   8
#define	MXC_F_QDEC_CTRL_STICKY   ((uint32_t)(0x1UL << MXC_F_QDEC_CTRL_STICKY_POS))
#define	MXC_F_QDEC_CTRL_PSC_POS   16
#define	MXC_F_QDEC_CTRL_PSC   ((uint32_t)(0x7UL << MXC_F_QDEC_CTRL_PSC_POS))
#define	MXC_V_QDEC_CTRL_PSC_DIV1   ((uint32_t)0x0UL)
#define	MXC_S_QDEC_CTRL_PSC_DIV1   (MXC_V_QDEC_CTRL_PSC_DIV1 << MXC_F_QDEC_CTRL_PSC_POS)
#define	MXC_V_QDEC_CTRL_PSC_DIV2   ((uint32_t)0x1UL)
#define	MXC_S_QDEC_CTRL_PSC_DIV2   (MXC_V_QDEC_CTRL_PSC_DIV2 << MXC_F_QDEC_CTRL_PSC_POS)
#define	MXC_V_QDEC_CTRL_PSC_DIV4   ((uint32_t)0x2UL)
#define	MXC_S_QDEC_CTRL_PSC_DIV4   (MXC_V_QDEC_CTRL_PSC_DIV4 << MXC_F_QDEC_CTRL_PSC_POS)
#define	MXC_V_QDEC_CTRL_PSC_DIV8   ((uint32_t)0x3UL)
#define	MXC_S_QDEC_CTRL_PSC_DIV8   (MXC_V_QDEC_CTRL_PSC_DIV8 << MXC_F_QDEC_CTRL_PSC_POS)
#define	MXC_V_QDEC_CTRL_PSC_DIV16   ((uint32_t)0x4UL)
#define	MXC_S_QDEC_CTRL_PSC_DIV16   (MXC_V_QDEC_CTRL_PSC_DIV16 << MXC_F_QDEC_CTRL_PSC_POS)
#define	MXC_V_QDEC_CTRL_PSC_DIV32   ((uint32_t)0x5UL)
#define	MXC_S_QDEC_CTRL_PSC_DIV32   (MXC_V_QDEC_CTRL_PSC_DIV32 << MXC_F_QDEC_CTRL_PSC_POS)
#define	MXC_V_QDEC_CTRL_PSC_DIV64   ((uint32_t)0x6UL)
#define	MXC_S_QDEC_CTRL_PSC_DIV64   (MXC_V_QDEC_CTRL_PSC_DIV64 << MXC_F_QDEC_CTRL_PSC_POS)
#define	MXC_V_QDEC_CTRL_PSC_DIV128   ((uint32_t)0x7UL)
#define	MXC_S_QDEC_CTRL_PSC_DIV128   (MXC_V_QDEC_CTRL_PSC_DIV128 << MXC_F_QDEC_CTRL_PSC_POS)

Detailed Description

Control Register.

Macro Definition Documentation

MXC_F_QDEC_CTRL_EN

#define MXC_F_QDEC_CTRL_EN   ((uint32_t)(0x1UL << MXC_F_QDEC_CTRL_EN_POS))

CTRL_EN Mask

MXC_F_QDEC_CTRL_EN_POS

#define MXC_F_QDEC_CTRL_EN_POS   0

CTRL_EN Position

MXC_F_QDEC_CTRL_FILTER

#define MXC_F_QDEC_CTRL_FILTER   ((uint32_t)(0x3UL << MXC_F_QDEC_CTRL_FILTER_POS))

CTRL_FILTER Mask

MXC_F_QDEC_CTRL_FILTER_POS

#define MXC_F_QDEC_CTRL_FILTER_POS   4

CTRL_FILTER Position

MXC_F_QDEC_CTRL_MODE

#define MXC_F_QDEC_CTRL_MODE   ((uint32_t)(0x3UL << MXC_F_QDEC_CTRL_MODE_POS))

CTRL_MODE Mask

MXC_F_QDEC_CTRL_MODE_POS

#define MXC_F_QDEC_CTRL_MODE_POS   1

CTRL_MODE Position

MXC_F_QDEC_CTRL_PSC

#define MXC_F_QDEC_CTRL_PSC   ((uint32_t)(0x7UL << MXC_F_QDEC_CTRL_PSC_POS))

CTRL_PSC Mask

MXC_F_QDEC_CTRL_PSC_POS

#define MXC_F_QDEC_CTRL_PSC_POS   16

CTRL_PSC Position

MXC_F_QDEC_CTRL_RST_INDEX

#define MXC_F_QDEC_CTRL_RST_INDEX   ((uint32_t)(0x1UL << MXC_F_QDEC_CTRL_RST_INDEX_POS))

CTRL_RST_INDEX Mask

MXC_F_QDEC_CTRL_RST_INDEX_POS

#define MXC_F_QDEC_CTRL_RST_INDEX_POS   6

CTRL_RST_INDEX Position

MXC_F_QDEC_CTRL_RST_MAXCNT

#define MXC_F_QDEC_CTRL_RST_MAXCNT   ((uint32_t)(0x1UL << MXC_F_QDEC_CTRL_RST_MAXCNT_POS))

CTRL_RST_MAXCNT Mask

MXC_F_QDEC_CTRL_RST_MAXCNT_POS

#define MXC_F_QDEC_CTRL_RST_MAXCNT_POS   7

CTRL_RST_MAXCNT Position

MXC_F_QDEC_CTRL_STICKY

#define MXC_F_QDEC_CTRL_STICKY   ((uint32_t)(0x1UL << MXC_F_QDEC_CTRL_STICKY_POS))

CTRL_STICKY Mask

MXC_F_QDEC_CTRL_STICKY_POS

#define MXC_F_QDEC_CTRL_STICKY_POS   8

CTRL_STICKY Position

MXC_F_QDEC_CTRL_SWAP

#define MXC_F_QDEC_CTRL_SWAP   ((uint32_t)(0x1UL << MXC_F_QDEC_CTRL_SWAP_POS))

CTRL_SWAP Mask

MXC_F_QDEC_CTRL_SWAP_POS

#define MXC_F_QDEC_CTRL_SWAP_POS   3

CTRL_SWAP Position

MXC_S_QDEC_CTRL_FILTER_1_SAMPLE

#define MXC_S_QDEC_CTRL_FILTER_1_SAMPLE   (MXC_V_QDEC_CTRL_FILTER_1_SAMPLE << MXC_F_QDEC_CTRL_FILTER_POS)

CTRL_FILTER_1_SAMPLE Setting

MXC_S_QDEC_CTRL_FILTER_2_SAMPLES

#define MXC_S_QDEC_CTRL_FILTER_2_SAMPLES   (MXC_V_QDEC_CTRL_FILTER_2_SAMPLES << MXC_F_QDEC_CTRL_FILTER_POS)

CTRL_FILTER_2_SAMPLES Setting

MXC_S_QDEC_CTRL_FILTER_3_SAMPLES

#define MXC_S_QDEC_CTRL_FILTER_3_SAMPLES   (MXC_V_QDEC_CTRL_FILTER_3_SAMPLES << MXC_F_QDEC_CTRL_FILTER_POS)

CTRL_FILTER_3_SAMPLES Setting

MXC_S_QDEC_CTRL_FILTER_4_SAMPLES

#define MXC_S_QDEC_CTRL_FILTER_4_SAMPLES   (MXC_V_QDEC_CTRL_FILTER_4_SAMPLES << MXC_F_QDEC_CTRL_FILTER_POS)

CTRL_FILTER_4_SAMPLES Setting

MXC_S_QDEC_CTRL_MODE_X1MODE

#define MXC_S_QDEC_CTRL_MODE_X1MODE   (MXC_V_QDEC_CTRL_MODE_X1MODE << MXC_F_QDEC_CTRL_MODE_POS)

CTRL_MODE_X1MODE Setting

MXC_S_QDEC_CTRL_MODE_X2MODE

#define MXC_S_QDEC_CTRL_MODE_X2MODE   (MXC_V_QDEC_CTRL_MODE_X2MODE << MXC_F_QDEC_CTRL_MODE_POS)

CTRL_MODE_X2MODE Setting

MXC_S_QDEC_CTRL_MODE_X4MODE

#define MXC_S_QDEC_CTRL_MODE_X4MODE   (MXC_V_QDEC_CTRL_MODE_X4MODE << MXC_F_QDEC_CTRL_MODE_POS)

CTRL_MODE_X4MODE Setting

MXC_S_QDEC_CTRL_PSC_DIV1

#define MXC_S_QDEC_CTRL_PSC_DIV1   (MXC_V_QDEC_CTRL_PSC_DIV1 << MXC_F_QDEC_CTRL_PSC_POS)

CTRL_PSC_DIV1 Setting

MXC_S_QDEC_CTRL_PSC_DIV128

#define MXC_S_QDEC_CTRL_PSC_DIV128   (MXC_V_QDEC_CTRL_PSC_DIV128 << MXC_F_QDEC_CTRL_PSC_POS)

CTRL_PSC_DIV128 Setting

MXC_S_QDEC_CTRL_PSC_DIV16

#define MXC_S_QDEC_CTRL_PSC_DIV16   (MXC_V_QDEC_CTRL_PSC_DIV16 << MXC_F_QDEC_CTRL_PSC_POS)

CTRL_PSC_DIV16 Setting

MXC_S_QDEC_CTRL_PSC_DIV2

#define MXC_S_QDEC_CTRL_PSC_DIV2   (MXC_V_QDEC_CTRL_PSC_DIV2 << MXC_F_QDEC_CTRL_PSC_POS)

CTRL_PSC_DIV2 Setting

MXC_S_QDEC_CTRL_PSC_DIV32

#define MXC_S_QDEC_CTRL_PSC_DIV32   (MXC_V_QDEC_CTRL_PSC_DIV32 << MXC_F_QDEC_CTRL_PSC_POS)

CTRL_PSC_DIV32 Setting

MXC_S_QDEC_CTRL_PSC_DIV4

#define MXC_S_QDEC_CTRL_PSC_DIV4   (MXC_V_QDEC_CTRL_PSC_DIV4 << MXC_F_QDEC_CTRL_PSC_POS)

CTRL_PSC_DIV4 Setting

MXC_S_QDEC_CTRL_PSC_DIV64

#define MXC_S_QDEC_CTRL_PSC_DIV64   (MXC_V_QDEC_CTRL_PSC_DIV64 << MXC_F_QDEC_CTRL_PSC_POS)

CTRL_PSC_DIV64 Setting

MXC_S_QDEC_CTRL_PSC_DIV8

#define MXC_S_QDEC_CTRL_PSC_DIV8   (MXC_V_QDEC_CTRL_PSC_DIV8 << MXC_F_QDEC_CTRL_PSC_POS)

CTRL_PSC_DIV8 Setting

MXC_V_QDEC_CTRL_FILTER_1_SAMPLE

#define MXC_V_QDEC_CTRL_FILTER_1_SAMPLE   ((uint32_t)0x0UL)

CTRL_FILTER_1_SAMPLE Value

MXC_V_QDEC_CTRL_FILTER_2_SAMPLES

#define MXC_V_QDEC_CTRL_FILTER_2_SAMPLES   ((uint32_t)0x1UL)

CTRL_FILTER_2_SAMPLES Value

MXC_V_QDEC_CTRL_FILTER_3_SAMPLES

#define MXC_V_QDEC_CTRL_FILTER_3_SAMPLES   ((uint32_t)0x2UL)

CTRL_FILTER_3_SAMPLES Value

MXC_V_QDEC_CTRL_FILTER_4_SAMPLES

#define MXC_V_QDEC_CTRL_FILTER_4_SAMPLES   ((uint32_t)0x3UL)

CTRL_FILTER_4_SAMPLES Value

MXC_V_QDEC_CTRL_MODE_X1MODE

#define MXC_V_QDEC_CTRL_MODE_X1MODE   ((uint32_t)0x0UL)

CTRL_MODE_X1MODE Value

MXC_V_QDEC_CTRL_MODE_X2MODE

#define MXC_V_QDEC_CTRL_MODE_X2MODE   ((uint32_t)0x1UL)

CTRL_MODE_X2MODE Value

MXC_V_QDEC_CTRL_MODE_X4MODE

#define MXC_V_QDEC_CTRL_MODE_X4MODE   ((uint32_t)0x2UL)

CTRL_MODE_X4MODE Value

MXC_V_QDEC_CTRL_PSC_DIV1

#define MXC_V_QDEC_CTRL_PSC_DIV1   ((uint32_t)0x0UL)

CTRL_PSC_DIV1 Value

MXC_V_QDEC_CTRL_PSC_DIV128

#define MXC_V_QDEC_CTRL_PSC_DIV128   ((uint32_t)0x7UL)

CTRL_PSC_DIV128 Value

MXC_V_QDEC_CTRL_PSC_DIV16

#define MXC_V_QDEC_CTRL_PSC_DIV16   ((uint32_t)0x4UL)

CTRL_PSC_DIV16 Value

MXC_V_QDEC_CTRL_PSC_DIV2

#define MXC_V_QDEC_CTRL_PSC_DIV2   ((uint32_t)0x1UL)

CTRL_PSC_DIV2 Value

MXC_V_QDEC_CTRL_PSC_DIV32

#define MXC_V_QDEC_CTRL_PSC_DIV32   ((uint32_t)0x5UL)

CTRL_PSC_DIV32 Value

MXC_V_QDEC_CTRL_PSC_DIV4

#define MXC_V_QDEC_CTRL_PSC_DIV4   ((uint32_t)0x2UL)

CTRL_PSC_DIV4 Value

MXC_V_QDEC_CTRL_PSC_DIV64

#define MXC_V_QDEC_CTRL_PSC_DIV64   ((uint32_t)0x6UL)

CTRL_PSC_DIV64 Value

MXC_V_QDEC_CTRL_PSC_DIV8

#define MXC_V_QDEC_CTRL_PSC_DIV8   ((uint32_t)0x3UL)

CTRL_PSC_DIV8 Value