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MAX32672 Peripheral Driver API
Peripheral Driver API for the MAX32672
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RTC Control Register.
#define MXC_F_RTC_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_BUSY_POS)) |
CTRL_BUSY Mask
#define MXC_F_RTC_CTRL_BUSY_POS 3 |
CTRL_BUSY Position
#define MXC_F_RTC_CTRL_EN ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_EN_POS)) |
CTRL_EN Mask
#define MXC_F_RTC_CTRL_EN_POS 0 |
CTRL_EN Position
#define MXC_F_RTC_CTRL_RD_EN ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RD_EN_POS)) |
CTRL_RD_EN Mask
#define MXC_F_RTC_CTRL_RD_EN_POS 14 |
CTRL_RD_EN Position
#define MXC_F_RTC_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDY_POS)) |
CTRL_RDY Mask
#define MXC_F_RTC_CTRL_RDY_IE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDY_IE_POS)) |
CTRL_RDY_IE Mask
#define MXC_F_RTC_CTRL_RDY_IE_POS 5 |
CTRL_RDY_IE Position
#define MXC_F_RTC_CTRL_RDY_POS 4 |
CTRL_RDY Position
#define MXC_F_RTC_CTRL_SQW_EN ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SQW_EN_POS)) |
CTRL_SQW_EN Mask
#define MXC_F_RTC_CTRL_SQW_EN_POS 8 |
CTRL_SQW_EN Position
#define MXC_F_RTC_CTRL_SQW_SEL ((uint32_t)(0x3UL << MXC_F_RTC_CTRL_SQW_SEL_POS)) |
CTRL_SQW_SEL Mask
#define MXC_F_RTC_CTRL_SQW_SEL_POS 9 |
CTRL_SQW_SEL Position
#define MXC_F_RTC_CTRL_SSEC_ALARM ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SSEC_ALARM_POS)) |
CTRL_SSEC_ALARM Mask
#define MXC_F_RTC_CTRL_SSEC_ALARM_IE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SSEC_ALARM_IE_POS)) |
CTRL_SSEC_ALARM_IE Mask
#define MXC_F_RTC_CTRL_SSEC_ALARM_IE_POS 2 |
CTRL_SSEC_ALARM_IE Position
#define MXC_F_RTC_CTRL_SSEC_ALARM_POS 7 |
CTRL_SSEC_ALARM Position
#define MXC_F_RTC_CTRL_TOD_ALARM ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_TOD_ALARM_POS)) |
CTRL_TOD_ALARM Mask
#define MXC_F_RTC_CTRL_TOD_ALARM_IE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_TOD_ALARM_IE_POS)) |
CTRL_TOD_ALARM_IE Mask
#define MXC_F_RTC_CTRL_TOD_ALARM_IE_POS 1 |
CTRL_TOD_ALARM_IE Position
#define MXC_F_RTC_CTRL_TOD_ALARM_POS 6 |
CTRL_TOD_ALARM Position
#define MXC_F_RTC_CTRL_WR_EN ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_WR_EN_POS)) |
CTRL_WR_EN Mask
#define MXC_F_RTC_CTRL_WR_EN_POS 15 |
CTRL_WR_EN Position
#define MXC_S_RTC_CTRL_SQW_SEL_CLKDIV8 (MXC_V_RTC_CTRL_SQW_SEL_CLKDIV8 << MXC_F_RTC_CTRL_SQW_SEL_POS) |
CTRL_SQW_SEL_CLKDIV8 Setting
#define MXC_S_RTC_CTRL_SQW_SEL_FREQ1HZ (MXC_V_RTC_CTRL_SQW_SEL_FREQ1HZ << MXC_F_RTC_CTRL_SQW_SEL_POS) |
CTRL_SQW_SEL_FREQ1HZ Setting
#define MXC_S_RTC_CTRL_SQW_SEL_FREQ4KHZ (MXC_V_RTC_CTRL_SQW_SEL_FREQ4KHZ << MXC_F_RTC_CTRL_SQW_SEL_POS) |
CTRL_SQW_SEL_FREQ4KHZ Setting
#define MXC_S_RTC_CTRL_SQW_SEL_FREQ512HZ (MXC_V_RTC_CTRL_SQW_SEL_FREQ512HZ << MXC_F_RTC_CTRL_SQW_SEL_POS) |
CTRL_SQW_SEL_FREQ512HZ Setting
#define MXC_V_RTC_CTRL_SQW_SEL_CLKDIV8 ((uint32_t)0x3UL) |
CTRL_SQW_SEL_CLKDIV8 Value
#define MXC_V_RTC_CTRL_SQW_SEL_FREQ1HZ ((uint32_t)0x0UL) |
CTRL_SQW_SEL_FREQ1HZ Value
#define MXC_V_RTC_CTRL_SQW_SEL_FREQ4KHZ ((uint32_t)0x2UL) |
CTRL_SQW_SEL_FREQ4KHZ Value
#define MXC_V_RTC_CTRL_SQW_SEL_FREQ512HZ ((uint32_t)0x1UL) |
CTRL_SQW_SEL_FREQ512HZ Value