SPI_INTEN

Macros
#define	MXC_F_SPI_INTEN_TX_THD_POS   0
#define	MXC_F_SPI_INTEN_TX_THD   ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_THD_POS))
#define	MXC_F_SPI_INTEN_TX_EM_POS   1
#define	MXC_F_SPI_INTEN_TX_EM   ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_EM_POS))
#define	MXC_F_SPI_INTEN_RX_THD_POS   2
#define	MXC_F_SPI_INTEN_RX_THD   ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_THD_POS))
#define	MXC_F_SPI_INTEN_RX_FULL_POS   3
#define	MXC_F_SPI_INTEN_RX_FULL   ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_FULL_POS))
#define	MXC_F_SPI_INTEN_SSA_POS   4
#define	MXC_F_SPI_INTEN_SSA   ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_SSA_POS))
#define	MXC_F_SPI_INTEN_SSD_POS   5
#define	MXC_F_SPI_INTEN_SSD   ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_SSD_POS))
#define	MXC_F_SPI_INTEN_FAULT_POS   8
#define	MXC_F_SPI_INTEN_FAULT   ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_FAULT_POS))
#define	MXC_F_SPI_INTEN_ABORT_POS   9
#define	MXC_F_SPI_INTEN_ABORT   ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_ABORT_POS))
#define	MXC_F_SPI_INTEN_MST_DONE_POS   11
#define	MXC_F_SPI_INTEN_MST_DONE   ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_MST_DONE_POS))
#define	MXC_F_SPI_INTEN_TX_OV_POS   12
#define	MXC_F_SPI_INTEN_TX_OV   ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_OV_POS))
#define	MXC_F_SPI_INTEN_TX_UN_POS   13
#define	MXC_F_SPI_INTEN_TX_UN   ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_UN_POS))
#define	MXC_F_SPI_INTEN_RX_OV_POS   14
#define	MXC_F_SPI_INTEN_RX_OV   ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_OV_POS))
#define	MXC_F_SPI_INTEN_RX_UN_POS   15
#define	MXC_F_SPI_INTEN_RX_UN   ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_UN_POS))

Detailed Description

Register for enabling interrupts.

Macro Definition Documentation

MXC_F_SPI_INTEN_ABORT

#define MXC_F_SPI_INTEN_ABORT   ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_ABORT_POS))

INTEN_ABORT Mask

MXC_F_SPI_INTEN_ABORT_POS

#define MXC_F_SPI_INTEN_ABORT_POS   9

INTEN_ABORT Position

MXC_F_SPI_INTEN_FAULT

#define MXC_F_SPI_INTEN_FAULT   ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_FAULT_POS))

INTEN_FAULT Mask

MXC_F_SPI_INTEN_FAULT_POS

#define MXC_F_SPI_INTEN_FAULT_POS   8

INTEN_FAULT Position

MXC_F_SPI_INTEN_MST_DONE

#define MXC_F_SPI_INTEN_MST_DONE   ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_MST_DONE_POS))

INTEN_MST_DONE Mask

MXC_F_SPI_INTEN_MST_DONE_POS

#define MXC_F_SPI_INTEN_MST_DONE_POS   11

INTEN_MST_DONE Position

MXC_F_SPI_INTEN_RX_FULL

#define MXC_F_SPI_INTEN_RX_FULL   ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_FULL_POS))

INTEN_RX_FULL Mask

MXC_F_SPI_INTEN_RX_FULL_POS

#define MXC_F_SPI_INTEN_RX_FULL_POS   3

INTEN_RX_FULL Position

MXC_F_SPI_INTEN_RX_OV

#define MXC_F_SPI_INTEN_RX_OV   ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_OV_POS))

INTEN_RX_OV Mask

MXC_F_SPI_INTEN_RX_OV_POS

#define MXC_F_SPI_INTEN_RX_OV_POS   14

INTEN_RX_OV Position

MXC_F_SPI_INTEN_RX_THD

#define MXC_F_SPI_INTEN_RX_THD   ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_THD_POS))

INTEN_RX_THD Mask

MXC_F_SPI_INTEN_RX_THD_POS

#define MXC_F_SPI_INTEN_RX_THD_POS   2

INTEN_RX_THD Position

MXC_F_SPI_INTEN_RX_UN

#define MXC_F_SPI_INTEN_RX_UN   ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_UN_POS))

INTEN_RX_UN Mask

MXC_F_SPI_INTEN_RX_UN_POS

#define MXC_F_SPI_INTEN_RX_UN_POS   15

INTEN_RX_UN Position

MXC_F_SPI_INTEN_SSA

#define MXC_F_SPI_INTEN_SSA   ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_SSA_POS))

INTEN_SSA Mask

MXC_F_SPI_INTEN_SSA_POS

#define MXC_F_SPI_INTEN_SSA_POS   4

INTEN_SSA Position

MXC_F_SPI_INTEN_SSD

#define MXC_F_SPI_INTEN_SSD   ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_SSD_POS))

INTEN_SSD Mask

MXC_F_SPI_INTEN_SSD_POS

#define MXC_F_SPI_INTEN_SSD_POS   5

INTEN_SSD Position

MXC_F_SPI_INTEN_TX_EM

#define MXC_F_SPI_INTEN_TX_EM   ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_EM_POS))

INTEN_TX_EM Mask

MXC_F_SPI_INTEN_TX_EM_POS

#define MXC_F_SPI_INTEN_TX_EM_POS   1

INTEN_TX_EM Position

MXC_F_SPI_INTEN_TX_OV

#define MXC_F_SPI_INTEN_TX_OV   ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_OV_POS))

INTEN_TX_OV Mask

MXC_F_SPI_INTEN_TX_OV_POS

#define MXC_F_SPI_INTEN_TX_OV_POS   12

INTEN_TX_OV Position

MXC_F_SPI_INTEN_TX_THD

#define MXC_F_SPI_INTEN_TX_THD   ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_THD_POS))

INTEN_TX_THD Mask

MXC_F_SPI_INTEN_TX_THD_POS

#define MXC_F_SPI_INTEN_TX_THD_POS   0

INTEN_TX_THD Position

MXC_F_SPI_INTEN_TX_UN

#define MXC_F_SPI_INTEN_TX_UN   ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_UN_POS))

INTEN_TX_UN Mask

MXC_F_SPI_INTEN_TX_UN_POS

#define MXC_F_SPI_INTEN_TX_UN_POS   13

INTEN_TX_UN Position