TMR_INTFL

Macros
#define	MXC_F_TMR_INTFL_IRQ_A_POS   0
#define	MXC_F_TMR_INTFL_IRQ_A   ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_IRQ_A_POS))
#define	MXC_F_TMR_INTFL_WRDONE_A_POS   8
#define	MXC_F_TMR_INTFL_WRDONE_A   ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WRDONE_A_POS))
#define	MXC_F_TMR_INTFL_WR_DIS_A_POS   9
#define	MXC_F_TMR_INTFL_WR_DIS_A   ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WR_DIS_A_POS))
#define	MXC_F_TMR_INTFL_IRQ_B_POS   16
#define	MXC_F_TMR_INTFL_IRQ_B   ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_IRQ_B_POS))
#define	MXC_F_TMR_INTFL_WRDONE_B_POS   24
#define	MXC_F_TMR_INTFL_WRDONE_B   ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WRDONE_B_POS))
#define	MXC_F_TMR_INTFL_WR_DIS_B_POS   25
#define	MXC_F_TMR_INTFL_WR_DIS_B   ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WR_DIS_B_POS))

Detailed Description

Timer Interrupt Status Register.

Macro Definition Documentation

MXC_F_TMR_INTFL_IRQ_A

#define MXC_F_TMR_INTFL_IRQ_A   ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_IRQ_A_POS))

INTFL_IRQ_A Mask

MXC_F_TMR_INTFL_IRQ_A_POS

#define MXC_F_TMR_INTFL_IRQ_A_POS   0

INTFL_IRQ_A Position

MXC_F_TMR_INTFL_IRQ_B

#define MXC_F_TMR_INTFL_IRQ_B   ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_IRQ_B_POS))

INTFL_IRQ_B Mask

MXC_F_TMR_INTFL_IRQ_B_POS

#define MXC_F_TMR_INTFL_IRQ_B_POS   16

INTFL_IRQ_B Position

MXC_F_TMR_INTFL_WR_DIS_A

#define MXC_F_TMR_INTFL_WR_DIS_A   ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WR_DIS_A_POS))

INTFL_WR_DIS_A Mask

MXC_F_TMR_INTFL_WR_DIS_A_POS

#define MXC_F_TMR_INTFL_WR_DIS_A_POS   9

INTFL_WR_DIS_A Position

MXC_F_TMR_INTFL_WR_DIS_B

#define MXC_F_TMR_INTFL_WR_DIS_B   ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WR_DIS_B_POS))

INTFL_WR_DIS_B Mask

MXC_F_TMR_INTFL_WR_DIS_B_POS

#define MXC_F_TMR_INTFL_WR_DIS_B_POS   25

INTFL_WR_DIS_B Position

MXC_F_TMR_INTFL_WRDONE_A

#define MXC_F_TMR_INTFL_WRDONE_A   ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WRDONE_A_POS))

INTFL_WRDONE_A Mask

MXC_F_TMR_INTFL_WRDONE_A_POS

#define MXC_F_TMR_INTFL_WRDONE_A_POS   8

INTFL_WRDONE_A Position

MXC_F_TMR_INTFL_WRDONE_B

#define MXC_F_TMR_INTFL_WRDONE_B   ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WRDONE_B_POS))

INTFL_WRDONE_B Mask

MXC_F_TMR_INTFL_WRDONE_B_POS

#define MXC_F_TMR_INTFL_WRDONE_B_POS   24

INTFL_WRDONE_B Position