Macros
#define	MXC_R_FLC_ADDR ((uint32_t)0x00000000UL)

#define	MXC_R_FLC_CLKDIV ((uint32_t)0x00000004UL)

#define	MXC_R_FLC_CTRL ((uint32_t)0x00000008UL)

#define	MXC_R_FLC_INTR ((uint32_t)0x00000024UL)

#define	MXC_R_FLC_ECCDATA ((uint32_t)0x00000028UL)

#define	MXC_R_FLC_DATA ((uint32_t)0x00000030UL)

#define	MXC_R_FLC_ACTRL ((uint32_t)0x00000040UL)

#define	MXC_R_FLC_WELR0 ((uint32_t)0x00000080UL)

#define	MXC_R_FLC_WELR1 ((uint32_t)0x00000088UL)

#define	MXC_R_FLC_RLR0 ((uint32_t)0x00000090UL)

#define	MXC_R_FLC_RLR1 ((uint32_t)0x00000098UL)

Detailed Description

FLC Peripheral Register Offsets from the FLC Base Peripheral Address.

Macro Definition Documentation

◆ MXC_R_FLC_ACTRL

#define MXC_R_FLC_ACTRL ((uint32_t)0x00000040UL)

Offset from FLC Base Address: 0x0040

◆ MXC_R_FLC_ADDR

#define MXC_R_FLC_ADDR ((uint32_t)0x00000000UL)

Offset from FLC Base Address: 0x0000

◆ MXC_R_FLC_CLKDIV

#define MXC_R_FLC_CLKDIV ((uint32_t)0x00000004UL)

Offset from FLC Base Address: 0x0004

◆ MXC_R_FLC_CTRL

#define MXC_R_FLC_CTRL ((uint32_t)0x00000008UL)

Offset from FLC Base Address: 0x0008

◆ MXC_R_FLC_DATA

#define MXC_R_FLC_DATA ((uint32_t)0x00000030UL)

Offset from FLC Base Address: 0x0030

◆ MXC_R_FLC_ECCDATA

#define MXC_R_FLC_ECCDATA ((uint32_t)0x00000028UL)

Offset from FLC Base Address: 0x0028

◆ MXC_R_FLC_INTR

#define MXC_R_FLC_INTR ((uint32_t)0x00000024UL)

Offset from FLC Base Address: 0x0024

◆ MXC_R_FLC_RLR0

#define MXC_R_FLC_RLR0 ((uint32_t)0x00000090UL)

Offset from FLC Base Address: 0x0090

◆ MXC_R_FLC_RLR1

#define MXC_R_FLC_RLR1 ((uint32_t)0x00000098UL)

Offset from FLC Base Address: 0x0098

◆ MXC_R_FLC_WELR0

#define MXC_R_FLC_WELR0 ((uint32_t)0x00000080UL)

Offset from FLC Base Address: 0x0080

◆ MXC_R_FLC_WELR1

#define MXC_R_FLC_WELR1 ((uint32_t)0x00000088UL)

Offset from FLC Base Address: 0x0088

Macros